sort out weirdness in FPDIVBasePipe initialisation

[ieee754fpu.git] / src / ieee754 / fpdiv / divstages.py

diff --git a/src/ieee754/fpdiv/divstages.py b/src/ieee754/fpdiv/divstages.py
index 6a65f0050b6f587f6d29b80feefbe83e8ce9f9ca..1b41b9e79dc0cdb84a61822acd3319e66705576e 100644 (file)
--- a/src/ieee754/fpdiv/divstages.py
+++ b/src/ieee754/fpdiv/divstages.py
@@ -12,6 +12,7 @@ from nmutil.singlepipe import (StageChain, SimpleHandshake)
 from ieee754.fpcommon.fpbase import FPState
 from ieee754.fpcommon.denorm import FPSCData
 from ieee754.fpcommon.postcalc import FPAddStage1Data
+from ieee754.div_rem_sqrt_rsqrt.div_pipe import DivPipeInterstageData
 
 # TODO: write these
 from .div0 import FPDivStage0Mod