more random experimenting

[ieee754fpu.git] / src / ieee754 / fpdiv / pipeline.py

diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index 1c137a821f7e0773727d809e095dab773ea89047..119db0f57f626438d4100e7a331d13cb125fc6b3 100644 (file)
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -81,25 +81,29 @@ class FPDIVBasePipe(ControlBase):
         ControlBase.__init__(self)
 
         pipechain = []
-        max_n_comb_stages = 2  # TODO (depends on how many RS's we want)
-        n_stages = pspec.fpformat.m_width // max_n_comb_stages
-        stage_idx = 0
+        max_n_comb_stages = 3  # TODO (depends on how many RS's we want)
         # to which the answer: "as few as possible"
         # is required.  too many ReservationStations
         # means "big problems".
 
+        # XXX BUG - subtracting 4 from number of stages stops assert
+        # probably related to having to add 4 in FPDivMuxInOut
+        radix = pspec.log2_radix
+        n_stages = pspec.core_config.n_stages // max_n_comb_stages
+        stage_idx = 0
+
         for i in range(n_stages):
 
             n_comb_stages = max_n_comb_stages
             # needs to convert input from pipestart ospec
             if i == 0:
                 kls = FPDivStagesSetup
-                n_comb_stages -= 1  # reduce due to work done at start
+                #n_comb_stages -= 1  # reduce due to work done at start?
 
             # needs to convert output to pipeend ispec
             elif i == n_stages - 1:
                 kls = FPDivStagesFinal
-                n_comb_stages -= 1  # FIXME - reduce due to work done at end?
+                #n_comb_stages -= 1  # FIXME - reduce due to work done at end?
 
             # intermediary stage
             else:
@@ -131,6 +135,9 @@ class FPDIVBasePipe(ControlBase):
 
         return m
 
+def roundup(x, mod):
+    return x if x % mod == 0 else x + mod - x % mod
+
 
 class FPDIVMuxInOut(ReservationStations):
     """ Reservation-Station version of FPDIV pipeline.
@@ -145,19 +152,21 @@ class FPDIVMuxInOut(ReservationStations):
                    then be used to change the behaviour of the pipeline.
     """
 
-    def __init__(self, width, num_rows, op_wid=0):
+    def __init__(self, width, num_rows, op_wid=1):
         self.id_wid = num_bits(width)
         self.pspec = PipelineSpec(width, self.id_wid, op_wid)
-        # get the standard mantissa width, store in the pspec
-        # (used in DivPipeBaseStage.get_core_config)
-        fpformat = FPFormat.standard(width)
+        # get the standard mantissa width, store in the pspec HOWEVER...
+        fmt = FPFormat.standard(width)
         log2_radix = 2
 
-        # 4 extra bits on the mantissa: MSB is zero, MSB-1 is 1
-        # then there is guard and round at the LSB end
-        cfg = DivPipeCoreConfig(width+4, fpformat.fraction_width, log2_radix)
+        # ...5 extra bits on the mantissa: MSB is zero, MSB-1 is 1
+        # then there is guard, round and sticky at the LSB end.
+        # also: round up to nearest radix
+        fmt.m_width = roundup(fmt.m_width + 5, log2_radix)
+
+        cfg = DivPipeCoreConfig(fmt.m_width, fmt.fraction_width, log2_radix)
 
-        self.pspec.fpformat = fpformat
+        self.pspec.fpformat = fmt
         self.pspec.log2_radix = log2_radix
         self.pspec.core_config = cfg