more random experimenting

[ieee754fpu.git] / src / ieee754 / fpdiv / pipeline.py

diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index 40bdedf64749adc6e4eb3b438c6096f79b9887a3..119db0f57f626438d4100e7a331d13cb125fc6b3 100644 (file)
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -81,7 +81,7 @@ class FPDIVBasePipe(ControlBase):
         ControlBase.__init__(self)
 
         pipechain = []
-        max_n_comb_stages = 2  # TODO (depends on how many RS's we want)
+        max_n_comb_stages = 3  # TODO (depends on how many RS's we want)
         # to which the answer: "as few as possible"
         # is required.  too many ReservationStations
         # means "big problems".
@@ -89,7 +89,7 @@ class FPDIVBasePipe(ControlBase):
         # XXX BUG - subtracting 4 from number of stages stops assert
         # probably related to having to add 4 in FPDivMuxInOut
         radix = pspec.log2_radix
-        n_stages = pspec.core_config.bit_width // (max_n_comb_stages * radix)
+        n_stages = pspec.core_config.n_stages // max_n_comb_stages
         stage_idx = 0
 
         for i in range(n_stages):
@@ -135,6 +135,9 @@ class FPDIVBasePipe(ControlBase):
 
         return m
 
+def roundup(x, mod):
+    return x if x % mod == 0 else x + mod - x % mod
+
 
 class FPDIVMuxInOut(ReservationStations):
     """ Reservation-Station version of FPDIV pipeline.
@@ -149,17 +152,18 @@ class FPDIVMuxInOut(ReservationStations):
                    then be used to change the behaviour of the pipeline.
     """
 
-    def __init__(self, width, num_rows, op_wid=0):
+    def __init__(self, width, num_rows, op_wid=1):
         self.id_wid = num_bits(width)
         self.pspec = PipelineSpec(width, self.id_wid, op_wid)
         # get the standard mantissa width, store in the pspec HOWEVER...
         fmt = FPFormat.standard(width)
-        # ...4 extra bits on the mantissa: MSB is zero, MSB-1 is 1
-        # then there is guard and round at the LSB end
-        fmt.m_width += 4
-        # TODO: make fmt.m_width a modulo of log2_radix
         log2_radix = 2
 
+        # ...5 extra bits on the mantissa: MSB is zero, MSB-1 is 1
+        # then there is guard, round and sticky at the LSB end.
+        # also: round up to nearest radix
+        fmt.m_width = roundup(fmt.m_width + 5, log2_radix)
+
         cfg = DivPipeCoreConfig(fmt.m_width, fmt.fraction_width, log2_radix)
 
         self.pspec.fpformat = fmt