rename FPADDBaseData to FPBaseData and move to separate module

[ieee754fpu.git] / src / ieee754 / fpdiv / pipeline.py

diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index c73d38148eb62bbd04f62359607e6106dc270e0d..3bbf3123ca6888b7033412a685b6245459beb493 100644 (file)
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -10,7 +10,7 @@ Relevant bugreports:
 
 Stack looks like this:
 
-scnorm   - FPDIVSpecialCasesDeNorm ispec FPADDBaseData
+scnorm   - FPDIVSpecialCasesDeNorm ispec FPBaseData
 ------                             ospec FPSCData
 
                 StageChain: FPDIVSpecialCasesMod,
@@ -35,7 +35,7 @@ pipediv1 - FPDivStagesIntermediate ispec DivPipeInterstageData
 ...
 
 pipediv5 - FPDivStageFinal         ispec FPDivStage0Data
---------                           ospec FPAddStage1Data
+--------                           ospec FPPostCalcData
 
                 StageChain: DivPipeCalculateStage,
                             ...
@@ -43,7 +43,7 @@ pipediv5 - FPDivStageFinal         ispec FPDivStage0Data
                             DivPipeFinalStage,
                             FPDivStage2Mod
 
-normpack - FPNormToPack            ispec FPAddStage1Data
+normpack - FPNormToPack            ispec FPPostCalcData
 --------                           ospec FPPackData
 
                 StageChain: Norm1ModSingle,
@@ -63,13 +63,10 @@ RS's.  that's far too many.  6 is just about an acceptable number.
 even 8 is starting to get alarmingly high.
 """
 
-from nmigen import Module
-from nmigen.cli import main, verilog
-
 from nmutil.singlepipe import ControlBase
 from nmutil.concurrentunit import ReservationStations, num_bits
 
-from ieee754.fpcommon.getop import FPADDBaseData
+from ieee754.fpcommon.basedata import FPBaseData
 from ieee754.fpcommon.denorm import FPSCData
 from ieee754.fpcommon.fpbase import FPFormat
 from ieee754.fpcommon.pack import FPPackData
@@ -152,7 +149,7 @@ def roundup(x, mod):
 class FPDIVMuxInOut(ReservationStations):
     """ Reservation-Station version of FPDIV pipeline.
 
-        * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
+        * fan-in on inputs (an array of FPBaseData: a,b,mid)
         * N-stage divider pipeline
         * fan-out on outputs (an array of FPPackData: z,mid)
 
@@ -193,7 +190,7 @@ class FPDIVMuxInOut(ReservationStations):
         ReservationStations.__init__(self, num_rows)
 
     def i_specfn(self):
-        return FPADDBaseData(self.pspec)
+        return FPBaseData(self.pspec)
 
     def o_specfn(self):
         return FPPackData(self.pspec)