reorganise loop

[ieee754fpu.git] / src / ieee754 / fpdiv / pipeline.py

diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index 13cac17b4edcc1dc1222bc833592a2e4b8d46bd5..cf2a04c20f774d110ba54a8cfcc574525e481ef7 100644 (file)
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -81,29 +81,34 @@ class FPDIVBasePipe(ControlBase):
         ControlBase.__init__(self)
 
         pipechain = []
-        n_stages = 6      # TODO (depends on width)
         n_comb_stages = 3  # TODO (depends on how many RS's we want)
-        stage_idx = 0
         # to which the answer: "as few as possible"
         # is required.  too many ReservationStations
         # means "big problems".
 
-        for i in range(n_stages):
+        # get number of stages, set up loop.
+        n_stages = pspec.core_config.n_stages
+        print ("n_stages", n_stages)
+        stage_idx = 0
+
+        end = False
+        while not end:
 
             # needs to convert input from pipestart ospec
-            if i == 0:
-                kls = FPDivStagesSetup
-                n_comb_stages -= 1  # reduce due to work done at start
+            if stage_idx == 0:
+                kls = FPDivStagesSetup # does n_comb_stages-1 calcs as well
 
             # needs to convert output to pipeend ispec
-            elif i == n_stages - 1:
-                kls = FPDivStagesFinal
-                n_comb_stages -= 1  # FIXME - reduce due to work done at end?
+            elif stage_idx + n_comb_stages >= n_stages:
+                kls = FPDivStagesFinal # does n_comb_stages-1 calcs as well
+                end = True
+                n_comb_stages = n_stages - stage_idx
 
             # intermediary stage
             else:
-                kls = FPDivStagesIntermediate
+                kls = FPDivStagesIntermediate # does n_comb_stages calcs
 
+            # create (in each pipe) a StageChain n_comb_stages in length
             pipechain.append(kls(self.pspec, n_comb_stages, stage_idx))
             stage_idx += n_comb_stages # increment so that each CalcStage
                                        # gets a (correct) unique index
@@ -130,6 +135,9 @@ class FPDIVBasePipe(ControlBase):
 
         return m
 
+def roundup(x, mod):
+    return x if x % mod == 0 else x + mod - x % mod
+
 
 class FPDIVMuxInOut(ReservationStations):
     """ Reservation-Station version of FPDIV pipeline.
@@ -144,15 +152,28 @@ class FPDIVMuxInOut(ReservationStations):
                    then be used to change the behaviour of the pipeline.
     """
 
-    def __init__(self, width, num_rows, op_wid=0):
+    def __init__(self, width, num_rows, op_wid=1):
         self.id_wid = num_bits(width)
         self.pspec = PipelineSpec(width, self.id_wid, op_wid)
-        # get the standard mantissa width, store in the pspec
-        # (used in DivPipeBaseStage.get_core_config)
-        fpformat = FPFormat.standard(width)
+        # get the standard mantissa width, store in the pspec HOWEVER...
+        fmt = FPFormat.standard(width)
         log2_radix = 2
-        cfg = DivPipeCoreConfig(width, fpformat.fraction_width, log2_radix)
-        self.pspec.fpformat = fpformat
+
+        # ...5 extra bits on the mantissa: MSB is zero, MSB-1 is 1
+        # then there is guard, round and sticky at the LSB end.
+        # also: round up to nearest radix
+        if width == 16:
+            extra = 5
+        elif width == 32:
+            extra = 6
+        elif width == 64:
+            extra = 5
+        fmt.m_width = roundup(fmt.m_width + extra, log2_radix)
+        print ("width", fmt.m_width)
+
+        cfg = DivPipeCoreConfig(fmt.m_width, fmt.fraction_width, log2_radix)
+
+        self.pspec.fpformat = fmt
         self.pspec.log2_radix = log2_radix
         self.pspec.core_config = cfg