add copyright / bugreport notice

[ieee754fpu.git] / src / ieee754 / fpdiv / specialcases.py

diff --git a/src/ieee754/fpdiv/specialcases.py b/src/ieee754/fpdiv/specialcases.py
index 75721de27ee9508e06e8b57ea30ef82d3c1673ba..e0c9b07843aafb2dc1bbd778341d3dce91ae4c11 100644 (file)
--- a/src/ieee754/fpdiv/specialcases.py
+++ b/src/ieee754/fpdiv/specialcases.py
@@ -1,4 +1,13 @@
-# IEEE Floating Point Multiplier
+""" IEEE Floating Point Divider
+
+Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Copyright (C) 2019 Jacob Lifshay
+
+Relevant bugreports:
+* http://bugs.libre-riscv.org/show_bug.cgi?id=99
+* http://bugs.libre-riscv.org/show_bug.cgi?id=43
+* http://bugs.libre-riscv.org/show_bug.cgi?id=44
+"""
 
 from nmigen import Module, Signal, Cat, Const, Elaboratable
 from nmigen.cli import main, verilog
@@ -65,6 +74,7 @@ class FPDIVSpecialCasesMod(Elaboratable):
         m.d.comb += abinf.eq(a1.is_inf & b1.is_inf)
 
         with m.If(self.i.ctx.op == 0):  # DIV
+
             # if a is NaN or b is NaN return NaN
             with m.If(abnan):
                 m.d.comb += self.o.out_do_z.eq(1)