rewrote the logic in div[02].py; fdiv/fsqrt/frsqrt all works!

[ieee754fpu.git] / src / ieee754 / fpdiv / test / test_fpdiv_pipe_32.py

diff --git a/src/ieee754/fpdiv/test/test_fpdiv_pipe_32.py b/src/ieee754/fpdiv/test/test_fpdiv_pipe_32.py
index d79eddce880b602e04837ea4b1b7a612fd12a9f8..91f3677fc9ef2f7c2cb0027fb2bd769af28d52e0 100644 (file)
--- a/src/ieee754/fpdiv/test/test_fpdiv_pipe_32.py
+++ b/src/ieee754/fpdiv/test/test_fpdiv_pipe_32.py
@@ -5,6 +5,7 @@ from ieee754.fpdiv.pipeline import (FPDIVMuxInOut,)
 from ieee754.fpcommon.test.case_gen import run_pipe_fp
 from ieee754.fpcommon.test import unit_test_single
 from ieee754.fpdiv.test.div_data32 import regressions
+from ieee754.div_rem_sqrt_rsqrt.core import DivPipeCoreOperation
 
 import unittest
 from sfpy import Float32
@@ -14,8 +15,10 @@ from operator import truediv as div
 class TestDivPipe(unittest.TestCase):
     def test_pipe_fp32(self):
         dut = FPDIVMuxInOut(32, 4)
+        # don't forget to initialize opcode; don't use magic numbers
+        opcode = int(DivPipeCoreOperation.UDivRem)
         run_pipe_fp(dut, 32, "div32", unit_test_single, Float32,
-                    regressions, div, 10)
+                    regressions, div, 10, opcode=opcode)
 
 
 if __name__ == '__main__':