format code

[ieee754fpu.git] / src / ieee754 / fpdiv / test / test_fprsqrt_pipe_16.py

diff --git a/src/ieee754/fpdiv/test/test_fprsqrt_pipe_16.py b/src/ieee754/fpdiv/test/test_fprsqrt_pipe_16.py
index 4ca5612276958b8ad9f0c78d3dc107b7ff531e8f..f02779de59581d920372f43b9bd3c338c4452c1b 100644 (file)
--- a/src/ieee754/fpdiv/test/test_fprsqrt_pipe_16.py
+++ b/src/ieee754/fpdiv/test/test_fprsqrt_pipe_16.py
@@ -1,7 +1,7 @@
 """ test of FPDIVMuxInOut
 """
 
-from ieee754.fpdiv.pipeline import (FPDIVMuxInOut,)
+from ieee754.fpdiv.pipeline import FPDIVMuxInOut
 from ieee754.fpcommon.test.case_gen import run_pipe_fp
 from ieee754.fpcommon.test import unit_test_half
 #from ieee754.fpdiv.test.rsqrt_data16 import regressions
@@ -25,5 +25,6 @@ class TestDivPipe(unittest.TestCase):
         run_pipe_fp(dut, 16, "rsqrt16", unit_test_half, Float16, None,
                     rsqrt, 100, single_op=True, opcode=opcode)
 
+
 if __name__ == '__main__':
     unittest.main()