cleanup on msb1 and align: use Mux, remove out_do_z

[ieee754fpu.git] / src / ieee754 / fpmul / mul0.py

diff --git a/src/ieee754/fpmul/mul0.py b/src/ieee754/fpmul/mul0.py
index 97821a65a182aa80cc972cf29fd1768c3f51d9a4..6b00762a33664eb508c8081b09aff7f5325cac2a 100644 (file)
--- a/src/ieee754/fpmul/mul0.py
+++ b/src/ieee754/fpmul/mul0.py
@@ -32,16 +32,14 @@ class FPMulStage0Mod(PipeModBase):
         # store intermediate tests (and zero-extended mantissas)
         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
-        comb += [
-                     am0.eq(Cat(self.i.a.m, 0)),
+        comb += [ am0.eq(Cat(self.i.a.m, 0)),
                      bm0.eq(Cat(self.i.b.m, 0))
-                    ]
-        # same-sign (both negative or both positive) mul mantissas
-        with m.If(~self.i.out_do_z):
-            comb += [self.o.z.e.eq(self.i.a.e + self.i.b.e + 1),
-                         self.o.product.eq(am0 * bm0 * 4),
-                         self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
                 ]
+        # same-sign (both negative or both positive) mul mantissas
+        comb += [self.o.z.e.eq(self.i.a.e + self.i.b.e + 1),
+                     self.o.product.eq(am0 * bm0 * 4),
+                     self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
+        ]
 
         comb += self.o.oz.eq(self.i.oz)
         comb += self.o.out_do_z.eq(self.i.out_do_z)