rename FPAddStage1Data to FPPostCalcData

[ieee754fpu.git] / src / ieee754 / fpmul / mul1.py

diff --git a/src/ieee754/fpmul/mul1.py b/src/ieee754/fpmul/mul1.py
index b83432ff3d771da2274a87b6e4f5f803737c7916..ce73ab2911af7d2165e6f3319920800255f789b1 100644 (file)
--- a/src/ieee754/fpmul/mul1.py
+++ b/src/ieee754/fpmul/mul1.py
@@ -8,7 +8,7 @@ from nmigen import Module, Signal
 from nmigen.cli import main, verilog
 
 from nmutil.pipemodbase import PipeModBase
-from ieee754.fpcommon.postcalc import FPAddStage1Data
+from ieee754.fpcommon.postcalc import FPPostCalcData
 from ieee754.fpmul.mul0 import FPMulStage0Data
 
 
@@ -23,7 +23,7 @@ class FPMulStage1Mod(PipeModBase):
         return FPMulStage0Data(self.pspec)
 
     def ospec(self):
-        return FPAddStage1Data(self.pspec)
+        return FPPostCalcData(self.pspec)
 
     def elaborate(self, platform):
         m = Module()