rename FPADDBaseData to FPBaseData and move to separate module

[ieee754fpu.git] / src / ieee754 / fpmul / pipeline.py

diff --git a/src/ieee754/fpmul/pipeline.py b/src/ieee754/fpmul/pipeline.py
index c20fa6253d3ff1ecb7e3f39319853a1d8a5fc575..dae5fbb4f3dcf779aa991d9d4fb50c9a4282957e 100644 (file)
--- a/src/ieee754/fpmul/pipeline.py
+++ b/src/ieee754/fpmul/pipeline.py
@@ -8,7 +8,7 @@ Stack looks like this:
 * mulstages - FPMulstages
 * normpack  - FPNormToPack
 
-scnorm   - FPDIVSpecialCasesDeNorm ispec FPADDBaseData
+scnorm   - FPDIVSpecialCasesDeNorm ispec FPBaseData
 ------                             ospec FPSCData
 
                 StageChain: FPMULSpecialCasesMod,
@@ -43,7 +43,7 @@ from nmigen.cli import main, verilog
 from nmutil.singlepipe import ControlBase
 from nmutil.concurrentunit import ReservationStations, num_bits
 
-from ieee754.fpcommon.getop import FPADDBaseData
+from ieee754.fpcommon.basedata import FPBaseData
 from ieee754.fpcommon.denorm import FPSCData
 from ieee754.fpcommon.pack import FPPackData
 from ieee754.fpcommon.normtopack import FPNormToPack
@@ -73,7 +73,7 @@ class FPMULBasePipe(ControlBase):
 class FPMULMuxInOut(ReservationStations):
     """ Reservation-Station version of FPMUL pipeline.
 
-        * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
+        * fan-in on inputs (an array of FPBaseData: a,b,mid)
         * 2-stage multiplier pipeline
         * fan-out on outputs (an array of FPPackData: z,mid)
 
@@ -88,7 +88,7 @@ class FPMULMuxInOut(ReservationStations):
         ReservationStations.__init__(self, num_rows)
 
     def i_specfn(self):
-        return FPADDBaseData(self.pspec)
+        return FPBaseData(self.pspec)
 
     def o_specfn(self):
         return FPPackData(self.pspec)