format code

[ieee754fpu.git] / src / ieee754 / fpmul / test / test_fpmul_pipe_64.py

diff --git a/src/ieee754/fpmul/test/test_fpmul_pipe_64.py b/src/ieee754/fpmul/test/test_fpmul_pipe_64.py
index 5670737ac9f4ba48aaa6bb496f08a89006536624..d348d2b01a9a04d8e1aa3ff46208fbb71de37298 100644 (file)
--- a/src/ieee754/fpmul/test/test_fpmul_pipe_64.py
+++ b/src/ieee754/fpmul/test/test_fpmul_pipe_64.py
@@ -1,7 +1,7 @@
 """ test of FPMULMuxInOut
 """
 
-from ieee754.fpmul.pipeline import (FPMULMuxInOut,)
+from ieee754.fpmul.pipeline import FPMULMuxInOut
 from ieee754.fpcommon.test.case_gen import run_pipe_fp
 from ieee754.fpcommon.test import unit_test_double
 from ieee754.fpmul.test.mul_data64 import regressions
@@ -13,7 +13,7 @@ from operator import mul
 def test_pipe_fp64():
     dut = FPMULMuxInOut(64, 4)
     run_pipe_fp(dut, 64, "mul", unit_test_double, Float64,
-                   regressions, mul, 10)
+                regressions, mul, 10)
 
 
 if __name__ == '__main__':