fix some borked imports

[ieee754fpu.git] / src / ieee754 / fpmul / test / test_mul64.py

diff --git a/src/ieee754/fpmul/test/test_mul64.py b/src/ieee754/fpmul/test/test_mul64.py
index 5f8eb305122abef76bbb094f448cf876df83b04e..93d624065eedbeee59ef1951a9d7863499171fde 100644 (file)
--- a/src/ieee754/fpmul/test/test_mul64.py
+++ b/src/ieee754/fpmul/test/test_mul64.py
@@ -2,18 +2,18 @@ from nmigen import Module, Signal
 from nmigen.compat.sim import run_simulation
 from operator import mul
 
-from fmul import FPMUL
+from ieee754.fpmul.fmul import FPMUL
 
 import sys
 import atexit
 from random import randint
 from random import seed
 
-from unit_test_double import (get_mantissa, get_exponent, get_sign, is_nan,
-                                is_inf, is_pos_inf, is_neg_inf,
-                                match, get_case, check_case, run_fpunit,
-                                run_edge_cases, run_corner_cases)
-
+from ieee754.fpcommon.test.unit_test_double import (
+    get_mantissa, get_exponent, get_sign, is_nan,
+    is_inf, is_pos_inf, is_neg_inf,
+    match, get_case, check_case, run_fpunit,
+    run_edge_cases, run_corner_cases)
 
 def testbench(dut):
     yield from check_case(dut, 0, 0, 0)