zero carry-in on __neg__
[ieee754fpu.git] / src / ieee754 / part / partsig.py
index 833451db99721ebf99329739145a3b847727c1ab..4a2e611baa8ba2cdbc1995dee9eb002442d474e2 100644 (file)
@@ -17,19 +17,21 @@ nmigen.Case, or other constructs: only Mux and other logic.
 """
 
 from ieee754.part_mul_add.adder import PartitionedAdder
-#from ieee754.part_cmp.equal_ortree import PartitionedEq
 from ieee754.part_cmp.eq_gt_ge import PartitionedEqGtGe
+from ieee754.part_shift.part_shift_dynamic import PartitionedDynamicShift
+from ieee754.part_shift.part_shift_scalar import PartitionedScalarShift
 from ieee754.part_mul_add.partpoints import make_partition
 from operator import or_, xor, and_, not_
 
-from nmigen import (Signal,
-                    )
+from nmigen import (Signal, Const)
+
 
 def getsig(op1):
     if isinstance(op1, PartitionedSignal):
         op1 = op1.sig
     return op1
 
+
 def applyop(op1, op2, op):
     return op(getsig(op1), getsig(op2))
 
@@ -37,10 +39,11 @@ def applyop(op1, op2, op):
 class PartitionedSignal:
     def __init__(self, mask, *args, **kwargs):
         self.sig = Signal(*args, **kwargs)
-        width = self.sig.shape()[0] # get signal width
-        self.partpoints = make_partition(mask, width) # create partition points
+        width = self.sig.shape()[0]  # get signal width
+        # create partition points
+        self.partpoints = make_partition(mask, width)
         self.modnames = {}
-        for name in ['add', 'eq', 'gt', 'ge']:
+        for name in ['add', 'eq', 'gt', 'ge', 'ls']:
             self.modnames[name] = 0
 
     def set_module(self, m):
@@ -48,7 +51,7 @@ class PartitionedSignal:
 
     def get_modname(self, category):
         self.modnames[category] += 1
-        return "%s%d" % (category, self.modnames[category])
+        return "%s_%d" % (category, self.modnames[category])
 
     def eq(self, val):
         return self.sig.eq(getsig(val))
@@ -61,7 +64,8 @@ class PartitionedSignal:
     # unary ops that require partitioning
 
     def __neg__(self):
-        result, _ = self.add_op(self, ~0, carry=0) # TODO, subop
+        z = Const(0, self.sig.shape())
+        result, _ = self.add_op(self, ~0, carry=z)  # TODO, subop
         return result
 
     # binary ops that don't require partitioning
@@ -89,15 +93,41 @@ class PartitionedSignal:
     # TODO: detect if the 2nd operand is a Const, a Signal or a
     # PartitionedSignal.  if it's a Const or a Signal, a global shift
     # can occur.  if it's a PartitionedSignal, that's much more interesting.
+    def ls_op(self, op1, op2, carry):
+        op1 = getsig(op1)
+        if isinstance(op2, Const) or isinstance(op2, Signal):
+            scalar = True
+            shape = op1.shape()
+            pa = PartitionedScalarShift(shape[0], self.partpoints)
+        else:
+            scalar = False
+            op2 = getsig(op2)
+            shape = op1.shape()
+            pa = PartitionedDynamicShift(shape[0], self.partpoints)
+        setattr(self.m.submodules, self.get_modname('ls'), pa)
+        comb = self.m.d.comb
+        if scalar:
+            comb += pa.data.eq(op1)
+            comb += pa.shifter.eq(op2)
+        else:
+            comb += pa.a.eq(op1)
+            comb += pa.b.eq(op2)
+        # XXX TODO: carry-in, carry-out
+        #comb += pa.carry_in.eq(carry)
+        return (pa.output, 0)
+
     def __lshift__(self, other):
-        raise NotImplementedError
-        return Operator("<<", [self, other])
+        result, _ = self.ls_op(self, other, carry=0)
+        return result
+
     def __rlshift__(self, other):
         raise NotImplementedError
         return Operator("<<", [other, self])
+
     def __rshift__(self, other):
         raise NotImplementedError
         return Operator(">>", [self, other])
+
     def __rrshift__(self, other):
         raise NotImplementedError
         return Operator(">>", [other, self])
@@ -127,22 +157,24 @@ class PartitionedSignal:
         return (pa.output, pa.carry_out)
 
     def __add__(self, other):
-        result, _ =self.add_op(self, other, carry=0)
+        result, _ = self.add_op(self, other, carry=0)
         return result
 
     def __radd__(self, other):
-        result, _ =self.add_op(other, self)
+        result, _ = self.add_op(other, self)
         return result
 
     def __sub__(self, other):
-        result, _ = self.sub_op(self, other) # TODO, subop
+        result, _ = self.sub_op(self, other)
         return result
+
     def __rsub__(self, other):
-        result, _ = self.sub_op(other, self) # TODO, subop
+        result, _ = self.sub_op(other, self)
         return result
 
     def __mul__(self, other):
         return Operator("*", [self, other])
+
     def __rmul__(self, other):
         return Operator("*", [other, self])
 
@@ -155,20 +187,24 @@ class PartitionedSignal:
             # completely by prohibiting such division operations.
             raise NotImplementedError(
                     "Division by a signed value is not supported")
+
     def __mod__(self, other):
         raise NotImplementedError
         other = Value.cast(other)
         other.__check_divisor()
         return Operator("%", [self, other])
+
     def __rmod__(self, other):
         raise NotImplementedError
         self.__check_divisor()
         return Operator("%", [other, self])
+
     def __floordiv__(self, other):
         raise NotImplementedError
         other = Value.cast(other)
         other.__check_divisor()
         return Operator("//", [self, other])
+
     def __rfloordiv__(self, other):
         raise NotImplementedError
         self.__check_divisor()
@@ -177,11 +213,11 @@ class PartitionedSignal:
     # binary comparison ops that need partitioning
 
     def _compare(self, width, op1, op2, opname, optype):
-        #print (opname, op1, op2)
+        # print (opname, op1, op2)
         pa = PartitionedEqGtGe(width, self.partpoints)
         setattr(self.m.submodules, self.get_modname(opname), pa)
         comb = self.m.d.comb
-        comb += pa.opcode.eq(optype) # set opcode
+        comb += pa.opcode.eq(optype)  # set opcode
         if isinstance(op1, PartitionedSignal):
             comb += pa.a.eq(op1.sig)
         else:
@@ -263,6 +299,7 @@ class PartitionedSignal:
             ``1`` if an odd number of bits are set, ``0`` if an
                   even number of bits are set.
         """
+        # XXXX TODO: return partition-mask-sized set of bits
         raise NotImplementedError
         return Operator("r^", [self])
 
@@ -275,6 +312,5 @@ class PartitionedSignal:
             ``0`` if ``premise`` is true and ``conclusion`` is not,
             ``1`` otherwise.
         """
+        # amazingly, this should actually work.
         return ~premise | conclusion
-
-