Fix PartitionedSignal.neg and its test case

[ieee754fpu.git] / src / ieee754 / part / test / test_partsig.py

diff --git a/src/ieee754/part/test/test_partsig.py b/src/ieee754/part/test/test_partsig.py
index 1669e2b96d853a619cc0ce7f5a13e81242f71aee..7d87eceebac77801362179bdb4a8ca50140ded55 100644 (file)
--- a/src/ieee754/part/test/test_partsig.py
+++ b/src/ieee754/part/test/test_partsig.py
@@ -41,10 +41,7 @@ def create_ilang(dut, traces, test_name):
 
 def create_simulator(module, traces, test_name):
     create_ilang(module, traces, test_name)
-    return Simulator(module,
-                     vcd_file=open(test_name + ".vcd", "w"),
-                     gtkw_file=open(test_name + ".gtkw", "w"),
-                     traces=traces)
+    return Simulator(module)
 
 
 # XXX this is for coriolis2 experimentation
@@ -183,13 +180,13 @@ class TestPartitionPoints(unittest.TestCase):
         part_mask = Signal(4)  # divide into 4-bits
         module = TestAddMod(width, part_mask)
 
-        sim = create_simulator(module,
-                               [part_mask,
-                                module.a.sig,
-                                module.b.sig,
-                                module.add_output,
-                                module.eq_output],
-                               "part_sig_add")
+        test_name = "part_sig_add"
+        traces = [part_mask,
+                  module.a.sig,
+                  module.b.sig,
+                  module.add_output,
+                  module.eq_output]
+        sim = create_simulator(module, traces, test_name)
 
         def async_process():
 
@@ -283,7 +280,10 @@ class TestPartitionPoints(unittest.TestCase):
                 return result, carry
 
             def test_neg_fn(carry_in, a, b, mask):
-                return test_add_fn(0, a, ~0, mask)
+                lsb = mask & ~(mask - 1)  # has only LSB of mask set
+                pos = lsb.bit_length() - 1  # find bit position
+                a = (a & mask) >> pos  # shift it to the beginning
+                return ((-a) << pos) & mask, 0  # negate and shift it back
 
             def test_op(msg_prefix, carry, test_fn, mod_attr, *mask_list):
                 rand_data = []
@@ -470,7 +470,11 @@ class TestPartitionPoints(unittest.TestCase):
             yield from test_muxop("4-bit", 0b1000, 0b0100, 0b0010, 0b0001)
 
         sim.add_process(async_process)
-        sim.run()
+        with sim.write_vcd(
+                vcd_file=open(test_name + ".vcd", "w"),
+                gtkw_file=open(test_name + ".gtkw", "w"),
+                traces=traces):
+            sim.run()
 
 
 if __name__ == '__main__':