modify reorder_bits to copy the MSB of the partition to each bit

[ieee754fpu.git] / src / ieee754 / part_cmp / eq_gt_ge.py

diff --git a/src/ieee754/part_cmp/eq_gt_ge.py b/src/ieee754/part_cmp/eq_gt_ge.py
index 0f2854d7e433f48a7386f24756d75a9f9138b89b..9772522a79d48774027ddb3e28166b30206f94ec 100644 (file)
--- a/src/ieee754/part_cmp/eq_gt_ge.py
+++ b/src/ieee754/part_cmp/eq_gt_ge.py
@@ -14,13 +14,19 @@ See:
 """
 
 from nmigen import Signal, Module, Elaboratable, Cat, C, Mux, Repl
-from nmigen.cli import main
+from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.cli import main, rtlil
 
 from ieee754.part_mul_add.partpoints import PartitionPoints
-from ieee754.part_cmp.experiments.gt_combiner import GTCombiner
+from ieee754.part_cmp.gt_combiner import GTCombiner
+from ieee754.part_cmp.reorder_results import ReorderResults
+from ieee754.part_cmp.ripple import RippleLSB
 
 
 class PartitionedEqGtGe(Elaboratable):
+    EQ = C(0b00, 2)
+    GT = C(0b01, 2)
+    GE = C(0b10, 2)
 
     # Expansion of the partitioned equals module to handle Greater
     # Than and Greater than or Equal to. The function being evaluated
@@ -38,15 +44,18 @@ class PartitionedEqGtGe(Elaboratable):
         self.partition_points = PartitionPoints(partition_points)
         self.mwidth = len(self.partition_points)+1
         self.output = Signal(self.mwidth, reset_less=True)
-        if not self.partition_points.fits_in_width(width):
-            raise ValueError("partition_points doesn't fit in width")
+        assert (self.partition_points.fits_in_width(width),
+                "partition_points doesn't fit in width")
 
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
         m.submodules.gtc = gtc = GTCombiner(self.mwidth)
 
-        # make a series of "eqs" and "gts", splitting a and b into partition chunks
+        m.submodules.reorder = reorder = ReorderResults(self.mwidth)
+
+        # make a series of "eqs" and "gts", splitting a and b into
+        # partition chunks
         eqs = Signal(self.mwidth, reset_less=True)
         eql = []
         gts = Signal(self.mwidth, reset_less=True)
@@ -58,13 +67,14 @@ class PartitionedEqGtGe(Elaboratable):
             end = keys[i]
             eql.append(self.a[start:end] == self.b[start:end])
             gtl.append(self.a[start:end] > self.b[start:end])
-            start = end # for next time round loop
+            start = end  # for next time round loop
         comb += eqs.eq(Cat(*eql))
         comb += gts.eq(Cat(*gtl))
 
-        # Signal to control the constant injected into the partition next to a closed gate
+        # control the constant injected into the partition
+        # next to a closed gate
         aux_input = Signal()
-        # Signal to enable or disable the gt input for the gt partition combiner
+        # enable or disable the gt input for the gt partition combiner
         gt_en = Signal()
 
         with m.Switch(self.opcode):
@@ -78,12 +88,53 @@ class PartitionedEqGtGe(Elaboratable):
                 comb += aux_input.eq(1)
                 comb += gt_en.eq(1)
 
+        results = Signal(self.mwidth, reset_less=True)
         comb += gtc.gates.eq(self.partition_points.as_sig())
         comb += gtc.eqs.eq(eqs)
         comb += gtc.gts.eq(gts)
         comb += gtc.aux_input.eq(aux_input)
         comb += gtc.gt_en.eq(gt_en)
-        comb += self.output.eq(gtc.outputs)
+        comb += results.eq(gtc.outputs)
+
+        comb += reorder.results_in.eq(results)
+        comb += reorder.gates.eq(self.partition_points.as_sig())
 
+        comb += self.output.eq(reorder.output)
 
         return m
+
+    def ports(self):
+        return [self.a, self.b, self.opcode,
+                self.partition_points.as_sig(),
+                self.output]
+
+if __name__ == "__main__":
+    from ieee754.part_mul_add.partpoints import make_partition
+    m = Module()
+    mask = Signal(4)
+    m.submodules.egg = egg = PartitionedEqGtGe(16, make_partition(mask, 16))
+
+    sim = Simulator(m)
+
+    def process():
+        yield mask.eq(0b010)
+        yield egg.a.eq(0xf000)
+        yield egg.b.eq(0)
+        yield egg.opcode.eq(0b00)
+        yield Delay(1e-6)
+        out = yield egg.output
+        print("out", bin(out))
+        yield mask.eq(0b111)
+        yield egg.a.eq(0x0000)
+        yield egg.b.eq(0)
+        yield Delay(1e-6)
+        yield mask.eq(0b010)
+        yield egg.a.eq(0x0000)
+        yield egg.b.eq(0)
+        yield Delay(1e-6)
+        out = yield egg.output
+        print("out", bin(out))
+
+    sim.add_process(process)
+    with sim.write_vcd("eq_gt_ge.vcd", "eq_gt_ge.gtkw", traces=egg.ports()):
+        sim.run()