modify reorder_bits to copy the MSB of the partition to each bit

[ieee754fpu.git] / src / ieee754 / part_cmp / eq_gt_ge.py

diff --git a/src/ieee754/part_cmp/eq_gt_ge.py b/src/ieee754/part_cmp/eq_gt_ge.py
index 7120ca1f0345a1f4e7c672c6da2cdb0669a09f65..9772522a79d48774027ddb3e28166b30206f94ec 100644 (file)
--- a/src/ieee754/part_cmp/eq_gt_ge.py
+++ b/src/ieee754/part_cmp/eq_gt_ge.py
@@ -15,10 +15,12 @@ See:
 
 from nmigen import Signal, Module, Elaboratable, Cat, C, Mux, Repl
 from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.cli import main
+from nmigen.cli import main, rtlil
 
 from ieee754.part_mul_add.partpoints import PartitionPoints
-from ieee754.part_cmp.experiments.gt_combiner import GTCombiner
+from ieee754.part_cmp.gt_combiner import GTCombiner
+from ieee754.part_cmp.reorder_results import ReorderResults
+from ieee754.part_cmp.ripple import RippleLSB
 
 
 class PartitionedEqGtGe(Elaboratable):
@@ -42,14 +44,16 @@ class PartitionedEqGtGe(Elaboratable):
         self.partition_points = PartitionPoints(partition_points)
         self.mwidth = len(self.partition_points)+1
         self.output = Signal(self.mwidth, reset_less=True)
-        if not self.partition_points.fits_in_width(width):
-            raise ValueError("partition_points doesn't fit in width")
+        assert (self.partition_points.fits_in_width(width),
+                "partition_points doesn't fit in width")
 
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
         m.submodules.gtc = gtc = GTCombiner(self.mwidth)
 
+        m.submodules.reorder = reorder = ReorderResults(self.mwidth)
+
         # make a series of "eqs" and "gts", splitting a and b into
         # partition chunks
         eqs = Signal(self.mwidth, reset_less=True)
@@ -63,7 +67,7 @@ class PartitionedEqGtGe(Elaboratable):
             end = keys[i]
             eql.append(self.a[start:end] == self.b[start:end])
             gtl.append(self.a[start:end] > self.b[start:end])
-            start = end # for next time round loop
+            start = end  # for next time round loop
         comb += eqs.eq(Cat(*eql))
         comb += gts.eq(Cat(*gtl))
 
@@ -84,12 +88,18 @@ class PartitionedEqGtGe(Elaboratable):
                 comb += aux_input.eq(1)
                 comb += gt_en.eq(1)
 
+        results = Signal(self.mwidth, reset_less=True)
         comb += gtc.gates.eq(self.partition_points.as_sig())
         comb += gtc.eqs.eq(eqs)
         comb += gtc.gts.eq(gts)
         comb += gtc.aux_input.eq(aux_input)
         comb += gtc.gt_en.eq(gt_en)
-        comb += self.output.eq(gtc.outputs)
+        comb += results.eq(gtc.outputs)
+
+        comb += reorder.results_in.eq(results)
+        comb += reorder.gates.eq(self.partition_points.as_sig())
+
+        comb += self.output.eq(reorder.output)
 
         return m
 
@@ -110,9 +120,10 @@ if __name__ == "__main__":
         yield mask.eq(0b010)
         yield egg.a.eq(0xf000)
         yield egg.b.eq(0)
+        yield egg.opcode.eq(0b00)
         yield Delay(1e-6)
         out = yield egg.output
-        print ("out", bin(out))
+        print("out", bin(out))
         yield mask.eq(0b111)
         yield egg.a.eq(0x0000)
         yield egg.b.eq(0)
@@ -122,7 +133,7 @@ if __name__ == "__main__":
         yield egg.b.eq(0)
         yield Delay(1e-6)
         out = yield egg.output
-        print ("out", bin(out))
+        print("out", bin(out))
 
     sim.add_process(process)
     with sim.write_vcd("eq_gt_ge.vcd", "eq_gt_ge.gtkw", traces=egg.ports()):