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deal with zero-width ShiftMask
[ieee754fpu.git]
/
src
/
ieee754
/
part_mul_add
/
adder.py
diff --git
a/src/ieee754/part_mul_add/adder.py
b/src/ieee754/part_mul_add/adder.py
index c02883c97b8dd9cd66532e26001335792e27aee4..e1849b4d25fc5ec4fc4473cc02b32f49dd5912b2 100644
(file)
--- a/
src/ieee754/part_mul_add/adder.py
+++ b/
src/ieee754/part_mul_add/adder.py
@@
-268,6
+268,6
@@
class PartitionedAdder(Elaboratable):
# in [the LSB of each partition].
comb += ripple.results_in.eq(carry_tmp)
comb += ripple.gates.eq(self.part_pts.as_sig())
-
comb
+= self.carry_out.eq(ripple.output)
+
m.d.sync
+= self.carry_out.eq(ripple.output)
return m