expanded_width += 1
expanded_width += 1
self._expanded_width = expanded_width
- self._expanded_a = Signal(expanded_width)
- self._expanded_b = Signal(expanded_width)
- self._expanded_output = Signal(expanded_width)
def elaborate(self, platform):
"""Elaborate this module."""
m = Module()
+
+ # intermediates
+ expanded_a = Signal(self._expanded_width)
+ expanded_b = Signal(self._expanded_width)
+ expanded_output = Signal(self._expanded_width)
+
expanded_index = 0
# store bits in a list, use Cat later. graphviz is much cleaner
al = []
if i in self.partition_points:
# add extra bit set to 0 + 0 for enabled partition points
# and 1 + 0 for disabled partition points
- ea.append(self._expanded_a[expanded_index])
+ ea.append(expanded_a[expanded_index])
al.append(~self.partition_points[i])
- eb.append(self._expanded_b[expanded_index])
+ eb.append(expanded_b[expanded_index])
bl.append(C(0))
expanded_index += 1
- ea.append(self._expanded_a[expanded_index])
+ ea.append(expanded_a[expanded_index])
al.append(self.a[i])
- eb.append(self._expanded_b[expanded_index])
+ eb.append(expanded_b[expanded_index])
bl.append(self.b[i])
- eo.append(self._expanded_output[expanded_index])
+ eo.append(expanded_output[expanded_index])
ol.append(self.output[i])
expanded_index += 1
# combine above using Cat
m.d.comb += Cat(*ol).eq(Cat(*eo))
# use only one addition to take advantage of look-ahead carry and
# special hardware on FPGAs
- m.d.comb += self._expanded_output.eq(
- self._expanded_a + self._expanded_b)
+ m.d.comb += expanded_output.eq( expanded_a + expanded_b)
return m
return value
-class Term(Elaboratable):
- def __init__(self, width, twidth, shift=0, enabled=None):
- self.width = width
- self.shift = shift
- self.enabled = enabled
- self.ti = Signal(width, reset_less=True)
- self.term = Signal(twidth, reset_less=True)
-
- def elaborate(self, platform):
-
- m = Module()
- m.d.comb += self.term.eq(get_term(self.ti, self.shift, self.enabled))
-
- return m
-
-
class ProductTerm(Elaboratable):
+
def __init__(self, width, twidth, pbwid, a_index, b_index):
self.a_index = a_index
self.b_index = b_index
shift = 8 * (self.a_index + self.b_index)
self.pwidth = width
- self.a = Signal(twidth, reset_less=True)
- self.b = Signal(twidth, reset_less=True)
+ self.width = width*2
+ self.shift = shift
+
+ self.ti = Signal(self.width, reset_less=True)
+ self.term = Signal(twidth, reset_less=True)
+ self.a = Signal(twidth//2, reset_less=True)
+ self.b = Signal(twidth//2, reset_less=True)
self.pb_en = Signal(pbwid, reset_less=True)
self.tl = tl = []
term_enabled = Signal(name=name, reset_less=True)
else:
term_enabled = None
-
- Term.__init__(self, width*2, twidth, shift, term_enabled)
+ self.enabled = term_enabled
self.term.name = "term_%d_%d" % (a_index, b_index) # rename
def elaborate(self, platform):
- m = Term.elaborate(self, platform)
+ m = Module()
if self.enabled is not None:
m.d.comb += self.enabled.eq(~(Cat(*self.tl).bool()))
m.d.comb += bsa.eq(self.a.bit_select(a_index * pwidth, pwidth))
m.d.comb += bsb.eq(self.b.bit_select(b_index * pwidth, pwidth))
m.d.comb += self.ti.eq(bsa * bsb)
+ m.d.comb += self.term.eq(get_term(self.ti, self.shift, self.enabled))
+
+ return m
+
+
+class ProductTerms(Elaboratable):
+
+ def __init__(self, width, twidth, pbwid, a_index, blen):
+ self.a_index = a_index
+ self.blen = blen
+ self.pwidth = width
+ self.twidth = twidth
+ self.pbwid = pbwid
+ self.a = Signal(twidth//2, reset_less=True)
+ self.b = Signal(twidth//2, reset_less=True)
+ self.pb_en = Signal(pbwid, reset_less=True)
+ self.terms = [Signal(twidth, name="term%d"%i, reset_less=True) \
+ for i in range(blen)]
+
+ def elaborate(self, platform):
+
+ m = Module()
+
+ for b_index in range(self.blen):
+ t = ProductTerm(self.pwidth, self.twidth, self.pbwid,
+ self.a_index, b_index)
+ setattr(m.submodules, "term_%d" % b_index, t)
+
+ m.d.comb += t.a.eq(self.a)
+ m.d.comb += t.b.eq(self.b)
+ m.d.comb += t.pb_en.eq(self.pb_en)
+
+ m.d.comb += self.terms[b_index].eq(t.term)
return m
# inputs
self.a = Signal(64)
self.b = Signal(64)
- self._a_signed = [Signal(name=f"_a_signed_{i}") for i in range(8)]
- self._b_signed = [Signal(name=f"_b_signed_{i}") for i in range(8)]
+ self.a_signed = [Signal(name=f"a_signed_{i}") for i in range(8)]
+ self.b_signed = [Signal(name=f"_b_signed_{i}") for i in range(8)]
self.pbs = Signal(pbwid, reset_less=True)
# outputs
self.parts = [Signal(name=f"part_{i}") for i in range(n_parts)]
self.delayed_parts = [
- [Signal(name=f"delayed_part_8_{delay}_{i}")
+ [Signal(name=f"delayed_part_{delay}_{i}")
for i in range(n_parts)]
for delay in range(n_levels)]
+ # XXX REALLY WEIRD BUG - have to take a copy of the last delayed_parts
+ self.dplast = [Signal(name=f"dplast_{i}")
+ for i in range(n_parts)]
self.not_a_term = Signal(width)
self.neg_lsb_a_term = Signal(width)
m.d.comb += delayed_parts[0][i].eq(parts[i])
m.d.sync += [delayed_parts[j + 1][i].eq(delayed_parts[j][i])
for j in range(len(delayed_parts)-1)]
+ m.d.comb += self.dplast[i].eq(delayed_parts[-1][i])
not_a_term, neg_lsb_a_term, not_b_term, neg_lsb_b_term = \
self.not_a_term, self.neg_lsb_a_term, \
nat, nbt, nla, nlb = [], [], [], []
for i in range(len(parts)):
be = parts[i] & self.a[(i + 1) * bit_width - 1] \
- & self._a_signed[i * byte_width]
+ & self.a_signed[i * byte_width]
ae = parts[i] & self.b[(i + 1) * bit_width - 1] \
- & self._b_signed[i * byte_width]
+ & self.b_signed[i * byte_width]
a_enabled = Signal(name="a_en_%d" % i, reset_less=True)
b_enabled = Signal(name="b_en_%d" % i, reset_less=True)
m.d.comb += a_enabled.eq(ae)
return m
+class IntermediateOut(Elaboratable):
+ def __init__(self, width, out_wid, n_parts):
+ self.width = width
+ self.n_parts = n_parts
+ self.delayed_part_ops = [Signal(2, name="dpop%d" % i, reset_less=True)
+ for i in range(8)]
+ self.intermed = Signal(out_wid, reset_less=True)
+ self.output = Signal(out_wid//2, reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ ol = []
+ w = self.width
+ sel = w // 8
+ for i in range(self.n_parts):
+ op = Signal(w, reset_less=True, name="op%d_%d" % (w, i))
+ m.d.comb += op.eq(
+ Mux(self.delayed_part_ops[sel * i] == OP_MUL_LOW,
+ self.intermed.bit_select(i * w*2, w),
+ self.intermed.bit_select(i * w*2 + w, w)))
+ ol.append(op)
+ m.d.comb += self.output.eq(Cat(*ol))
+
+ return m
+
+
+class FinalOut(Elaboratable):
+ def __init__(self, out_wid):
+ # inputs
+ self.d8 = [Signal(name=f"d8_{i}", reset_less=True) for i in range(8)]
+ self.d16 = [Signal(name=f"d16_{i}", reset_less=True) for i in range(4)]
+ self.d32 = [Signal(name=f"d32_{i}", reset_less=True) for i in range(2)]
+
+ self.i8 = Signal(out_wid, reset_less=True)
+ self.i16 = Signal(out_wid, reset_less=True)
+ self.i32 = Signal(out_wid, reset_less=True)
+ self.i64 = Signal(out_wid, reset_less=True)
+
+ # output
+ self.out = Signal(out_wid, reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+ ol = []
+ for i in range(8):
+ op = Signal(8, reset_less=True, name="op_%d" % i)
+ m.d.comb += op.eq(
+ Mux(self.d8[i] | self.d16[i // 2],
+ Mux(self.d8[i], self.i8.bit_select(i * 8, 8),
+ self.i16.bit_select(i * 8, 8)),
+ Mux(self.d32[i // 4], self.i32.bit_select(i * 8, 8),
+ self.i64.bit_select(i * 8, 8))))
+ ol.append(op)
+ m.d.comb += self.out.eq(Cat(*ol))
+ return m
+
+
+class OrMod(Elaboratable):
+ def __init__(self, wid):
+ self.wid = wid
+ self.orin = [Signal(wid, name="orin%d" % i, reset_less=True)
+ for i in range(4)]
+ self.orout = Signal(wid, reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+ or1 = Signal(self.wid, reset_less=True)
+ or2 = Signal(self.wid, reset_less=True)
+ m.d.comb += or1.eq(self.orin[0] | self.orin[1])
+ m.d.comb += or2.eq(self.orin[2] | self.orin[3])
+ m.d.comb += self.orout.eq(or1 | or2)
+
+ return m
+
+
+class Signs(Elaboratable):
+
+ def __init__(self):
+ self.part_ops = Signal(2, reset_less=True)
+ self.a_signed = Signal(reset_less=True)
+ self.b_signed = Signal(reset_less=True)
+
+ def elaborate(self, platform):
+
+ m = Module()
+
+ asig = self.part_ops != OP_MUL_UNSIGNED_HIGH
+ bsig = (self.part_ops == OP_MUL_LOW) \
+ | (self.part_ops == OP_MUL_SIGNED_HIGH)
+ m.d.comb += self.a_signed.eq(asig)
+ m.d.comb += self.b_signed.eq(bsig)
+
+ return m
+
+
class Mul8_16_32_64(Elaboratable):
"""Signed/Unsigned 8/16/32/64-bit partitioned integer multiplier.
"""
def __init__(self, register_levels= ()):
+
+ # parameter(s)
+ self.register_levels = list(register_levels)
+
+ # inputs
self.part_pts = PartitionPoints()
for i in range(8, 64, 8):
self.part_pts[i] = Signal(name=f"part_pts_{i}")
self.part_ops = [Signal(2, name=f"part_ops_{i}") for i in range(8)]
self.a = Signal(64)
self.b = Signal(64)
- self.output = Signal(64)
- self.register_levels = list(register_levels)
+
+ # intermediates (needed for unit tests)
self._intermediate_output = Signal(128)
- self._output_64 = Signal(64)
- self._output_32 = Signal(64)
- self._output_16 = Signal(64)
- self._output_8 = Signal(64)
- self._a_signed = [Signal(name=f"_a_signed_{i}") for i in range(8)]
- self._b_signed = [Signal(name=f"_b_signed_{i}") for i in range(8)]
+
+ # output
+ self.output = Signal(64)
def _part_byte(self, index):
if index == -1 or index == 7:
tl.append(pb)
m.d.comb += pbs.eq(Cat(*tl))
+ # local variables
+ signs = []
+ for i in range(8):
+ s = Signs()
+ signs.append(s)
+ setattr(m.submodules, "signs%d" % i, s)
+ m.d.comb += s.part_ops.eq(self.part_ops[i])
+
delayed_part_ops = [
[Signal(2, name=f"_delayed_part_ops_{delay}_{i}")
for i in range(8)]
for delay in range(1 + len(self.register_levels))]
for i in range(len(self.part_ops)):
m.d.comb += delayed_part_ops[0][i].eq(self.part_ops[i])
- m.d.sync += [delayed_part_ops[j + 1][i]
- .eq(delayed_part_ops[j][i])
+ m.d.sync += [delayed_part_ops[j + 1][i].eq(delayed_part_ops[j][i])
for j in range(len(self.register_levels))]
n_levels = len(self.register_levels)+1
for mod in [part_8, part_16, part_32, part_64]:
m.d.comb += mod.a.eq(self.a)
m.d.comb += mod.b.eq(self.b)
- for i in range(len(self._a_signed)):
- m.d.comb += mod._a_signed[i].eq(self._a_signed[i])
- for i in range(len(self._b_signed)):
- m.d.comb += mod._b_signed[i].eq(self._b_signed[i])
+ for i in range(len(signs)):
+ m.d.comb += mod.a_signed[i].eq(signs[i].a_signed)
+ m.d.comb += mod.b_signed[i].eq(signs[i].b_signed)
m.d.comb += mod.pbs.eq(pbs)
nat_l.append(mod.not_a_term)
nbt_l.append(mod.not_b_term)
terms = []
for a_index in range(8):
- for b_index in range(8):
- t = ProductTerm(8, 128, 8, a_index, b_index)
- setattr(m.submodules, "term_%d_%d" % (a_index, b_index), t)
+ t = ProductTerms(8, 128, 8, a_index, 8)
+ setattr(m.submodules, "terms_%d" % a_index, t)
- m.d.comb += t.a.eq(self.a)
- m.d.comb += t.b.eq(self.b)
- m.d.comb += t.pb_en.eq(pbs)
+ m.d.comb += t.a.eq(self.a)
+ m.d.comb += t.b.eq(self.b)
+ m.d.comb += t.pb_en.eq(pbs)
- terms.append(t.term)
+ for term in t.terms:
+ terms.append(term)
- for i in range(8):
- a_signed = self.part_ops[i] != OP_MUL_UNSIGNED_HIGH
- b_signed = (self.part_ops[i] == OP_MUL_LOW) \
- | (self.part_ops[i] == OP_MUL_SIGNED_HIGH)
- m.d.comb += self._a_signed[i].eq(a_signed)
- m.d.comb += self._b_signed[i].eq(b_signed)
-
- # it's fine to bitwise-or these together since they are never enabled
+ # it's fine to bitwise-or data together since they are never enabled
# at the same time
- nat_l = reduce(or_, nat_l)
- nbt_l = reduce(or_, nbt_l)
- nla_l = reduce(or_, nla_l)
- nlb_l = reduce(or_, nlb_l)
- m.submodules.nat = nat = Term(128, 128)
- m.submodules.nla = nla = Term(128, 128)
- m.submodules.nbt = nbt = Term(128, 128)
- m.submodules.nlb = nlb = Term(128, 128)
- m.d.comb += nat.ti.eq(nat_l)
- m.d.comb += nbt.ti.eq(nbt_l)
- m.d.comb += nla.ti.eq(nla_l)
- m.d.comb += nlb.ti.eq(nlb_l)
- terms.append(nat.term)
- terms.append(nla.term)
- terms.append(nbt.term)
- terms.append(nlb.term)
+ m.submodules.nat_or = nat_or = OrMod(128)
+ m.submodules.nbt_or = nbt_or = OrMod(128)
+ m.submodules.nla_or = nla_or = OrMod(128)
+ m.submodules.nlb_or = nlb_or = OrMod(128)
+ for l, mod in [(nat_l, nat_or),
+ (nbt_l, nbt_or),
+ (nla_l, nla_or),
+ (nlb_l, nlb_or)]:
+ for i in range(len(l)):
+ m.d.comb += mod.orin[i].eq(l[i])
+ terms.append(mod.orout)
expanded_part_pts = PartitionPoints()
for i, v in self.part_pts.items():
expanded_part_pts)
m.submodules.add_reduce = add_reduce
m.d.comb += self._intermediate_output.eq(add_reduce.output)
- m.d.comb += self._output_64.eq(
- Mux(delayed_part_ops[-1][0] == OP_MUL_LOW,
- self._intermediate_output.bit_select(0, 64),
- self._intermediate_output.bit_select(64, 64)))
+ # create _output_64
+ m.submodules.io64 = io64 = IntermediateOut(64, 128, 1)
+ m.d.comb += io64.intermed.eq(self._intermediate_output)
+ for i in range(8):
+ m.d.comb += io64.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
# create _output_32
- ol = []
- for i in range(2):
- op = Signal(32, reset_less=True, name="op32_%d" % i)
- m.d.comb += op.eq(
- Mux(delayed_part_ops[-1][4 * i] == OP_MUL_LOW,
- self._intermediate_output.bit_select(i * 64, 32),
- self._intermediate_output.bit_select(i * 64 + 32, 32)))
- ol.append(op)
- m.d.comb += self._output_32.eq(Cat(*ol))
+ m.submodules.io32 = io32 = IntermediateOut(32, 128, 2)
+ m.d.comb += io32.intermed.eq(self._intermediate_output)
+ for i in range(8):
+ m.d.comb += io32.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
# create _output_16
- ol = []
- for i in range(4):
- op = Signal(16, reset_less=True, name="op16_%d" % i)
- m.d.comb += op.eq(
- Mux(delayed_part_ops[-1][2 * i] == OP_MUL_LOW,
- self._intermediate_output.bit_select(i * 32, 16),
- self._intermediate_output.bit_select(i * 32 + 16, 16)))
- ol.append(op)
- m.d.comb += self._output_16.eq(Cat(*ol))
+ m.submodules.io16 = io16 = IntermediateOut(16, 128, 4)
+ m.d.comb += io16.intermed.eq(self._intermediate_output)
+ for i in range(8):
+ m.d.comb += io16.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
# create _output_8
- ol = []
+ m.submodules.io8 = io8 = IntermediateOut(8, 128, 8)
+ m.d.comb += io8.intermed.eq(self._intermediate_output)
for i in range(8):
- op = Signal(8, reset_less=True, name="op8_%d" % i)
- m.d.comb += op.eq(
- Mux(delayed_part_ops[-1][i] == OP_MUL_LOW,
- self._intermediate_output.bit_select(i * 16, 8),
- self._intermediate_output.bit_select(i * 16 + 8, 8)))
- ol.append(op)
- m.d.comb += self._output_8.eq(Cat(*ol))
+ m.d.comb += io8.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
# final output
- ol = []
- for i in range(8):
- op = Signal(8, reset_less=True, name="op%d" % i)
- m.d.comb += op.eq(
- Mux(part_8.delayed_parts[-1][i]
- | part_16.delayed_parts[-1][i // 2],
- Mux(part_8.delayed_parts[-1][i],
- self._output_8.bit_select(i * 8, 8),
- self._output_16.bit_select(i * 8, 8)),
- Mux(part_32.delayed_parts[-1][i // 4],
- self._output_32.bit_select(i * 8, 8),
- self._output_64.bit_select(i * 8, 8))))
- ol.append(op)
- m.d.comb += self.output.eq(Cat(*ol))
+ m.submodules.fo = fo = FinalOut(64)
+ for i in range(len(part_8.delayed_parts[-1])):
+ m.d.comb += fo.d8[i].eq(part_8.dplast[i])
+ for i in range(len(part_16.delayed_parts[-1])):
+ m.d.comb += fo.d16[i].eq(part_16.dplast[i])
+ for i in range(len(part_32.delayed_parts[-1])):
+ m.d.comb += fo.d32[i].eq(part_32.dplast[i])
+ m.d.comb += fo.i8.eq(io8.output)
+ m.d.comb += fo.i16.eq(io16.output)
+ m.d.comb += fo.i32.eq(io32.output)
+ m.d.comb += fo.i64.eq(io64.output)
+ m.d.comb += self.output.eq(fo.out)
+
return m
projects / ieee754fpu.git / blobdiff