expanded_width += 1
expanded_width += 1
self._expanded_width = expanded_width
- self._expanded_a = Signal(expanded_width)
- self._expanded_b = Signal(expanded_width)
- self._expanded_output = Signal(expanded_width)
def elaborate(self, platform):
"""Elaborate this module."""
m = Module()
+
+ # intermediates
+ expanded_a = Signal(self._expanded_width)
+ expanded_b = Signal(self._expanded_width)
+ expanded_output = Signal(self._expanded_width)
+
expanded_index = 0
# store bits in a list, use Cat later. graphviz is much cleaner
al = []
if i in self.partition_points:
# add extra bit set to 0 + 0 for enabled partition points
# and 1 + 0 for disabled partition points
- ea.append(self._expanded_a[expanded_index])
+ ea.append(expanded_a[expanded_index])
al.append(~self.partition_points[i])
- eb.append(self._expanded_b[expanded_index])
+ eb.append(expanded_b[expanded_index])
bl.append(C(0))
expanded_index += 1
- ea.append(self._expanded_a[expanded_index])
+ ea.append(expanded_a[expanded_index])
al.append(self.a[i])
- eb.append(self._expanded_b[expanded_index])
+ eb.append(expanded_b[expanded_index])
bl.append(self.b[i])
- eo.append(self._expanded_output[expanded_index])
+ eo.append(expanded_output[expanded_index])
ol.append(self.output[i])
expanded_index += 1
# combine above using Cat
m.d.comb += Cat(*ol).eq(Cat(*eo))
# use only one addition to take advantage of look-ahead carry and
# special hardware on FPGAs
- m.d.comb += self._expanded_output.eq(
- self._expanded_a + self._expanded_b)
+ m.d.comb += expanded_output.eq( expanded_a + expanded_b)
return m
return value
-class Term(Elaboratable):
- def __init__(self, width, twidth, shift=0, enabled=None):
- self.width = width
- self.shift = shift
- self.enabled = enabled
- self.ti = Signal(width, reset_less=True)
- self.term = Signal(twidth, reset_less=True)
-
- def elaborate(self, platform):
-
- m = Module()
- m.d.comb += self.term.eq(get_term(self.ti, self.shift, self.enabled))
-
- return m
-
-
class ProductTerm(Elaboratable):
+
def __init__(self, width, twidth, pbwid, a_index, b_index):
self.a_index = a_index
self.b_index = b_index
shift = 8 * (self.a_index + self.b_index)
self.pwidth = width
+ self.width = width*2
+ self.shift = shift
+
+ self.ti = Signal(self.width, reset_less=True)
+ self.term = Signal(twidth, reset_less=True)
self.a = Signal(twidth//2, reset_less=True)
self.b = Signal(twidth//2, reset_less=True)
self.pb_en = Signal(pbwid, reset_less=True)
term_enabled = Signal(name=name, reset_less=True)
else:
term_enabled = None
-
- Term.__init__(self, width*2, twidth, shift, term_enabled)
+ self.enabled = term_enabled
self.term.name = "term_%d_%d" % (a_index, b_index) # rename
def elaborate(self, platform):
- m = Term.elaborate(self, platform)
+ m = Module()
if self.enabled is not None:
m.d.comb += self.enabled.eq(~(Cat(*self.tl).bool()))
m.d.comb += bsa.eq(self.a.bit_select(a_index * pwidth, pwidth))
m.d.comb += bsb.eq(self.b.bit_select(b_index * pwidth, pwidth))
m.d.comb += self.ti.eq(bsa * bsb)
+ m.d.comb += self.term.eq(get_term(self.ti, self.shift, self.enabled))
return m
# outputs
self.parts = [Signal(name=f"part_{i}") for i in range(n_parts)]
self.delayed_parts = [
- [Signal(name=f"delayed_part_8_{delay}_{i}")
+ [Signal(name=f"delayed_part_{delay}_{i}")
for i in range(n_parts)]
for delay in range(n_levels)]
+ # XXX REALLY WEIRD BUG - have to take a copy of the last delayed_parts
+ self.dplast = [Signal(name=f"dplast_{i}")
+ for i in range(n_parts)]
self.not_a_term = Signal(width)
self.neg_lsb_a_term = Signal(width)
m.d.comb += delayed_parts[0][i].eq(parts[i])
m.d.sync += [delayed_parts[j + 1][i].eq(delayed_parts[j][i])
for j in range(len(delayed_parts)-1)]
+ m.d.comb += self.dplast[i].eq(delayed_parts[-1][i])
not_a_term, neg_lsb_a_term, not_b_term, neg_lsb_b_term = \
self.not_a_term, self.neg_lsb_a_term, \
class FinalOut(Elaboratable):
def __init__(self, out_wid):
# inputs
- self.d8 = [Signal(name=f"d8{i}") for i in range(8)]
- self.d16 = [Signal(name=f"d16{i}") for i in range(4)]
- self.d32 = [Signal(name=f"d32{i}") for i in range(2)]
- self.out8 = Signal(out_wid, reset_less=True)
- self.out16 = Signal(out_wid, reset_less=True)
- self.out32 = Signal(out_wid, reset_less=True)
- self.out64 = Signal(out_wid, reset_less=True)
+ self.d8 = [Signal(name=f"d8_{i}", reset_less=True) for i in range(8)]
+ self.d16 = [Signal(name=f"d16_{i}", reset_less=True) for i in range(4)]
+ self.d32 = [Signal(name=f"d32_{i}", reset_less=True) for i in range(2)]
+
+ self.i8 = Signal(out_wid, reset_less=True)
+ self.i16 = Signal(out_wid, reset_less=True)
+ self.i32 = Signal(out_wid, reset_less=True)
+ self.i64 = Signal(out_wid, reset_less=True)
# output
- self.output = Signal(out_wid, reset_less=True)
+ self.out = Signal(out_wid, reset_less=True)
def elaborate(self, platform):
m = Module()
ol = []
for i in range(8):
- op = Signal(8, reset_less=True, name="op%d" % i)
+ op = Signal(8, reset_less=True, name="op_%d" % i)
m.d.comb += op.eq(
Mux(self.d8[i] | self.d16[i // 2],
- Mux(self.d8[i], self.out8.bit_select(i * 8, 8),
- self.out16.bit_select(i * 8, 8)),
- Mux(self.d32[i // 4], self.out32.bit_select(i * 8, 8),
- self.out64.bit_select(i * 8, 8))))
+ Mux(self.d8[i], self.i8.bit_select(i * 8, 8),
+ self.i16.bit_select(i * 8, 8)),
+ Mux(self.d32[i // 4], self.i32.bit_select(i * 8, 8),
+ self.i64.bit_select(i * 8, 8))))
ol.append(op)
- m.d.comb += self.output.eq(Cat(*ol))
+ m.d.comb += self.out.eq(Cat(*ol))
return m
m.d.comb += io8.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
# final output
- m.submodules.finalout = out = FinalOut(64)
- for i in range(8):
- m.d.comb += out.d8[i].eq(part_8.delayed_parts[-1][i])
- for i in range(4):
- m.d.comb += out.d16[i].eq(part_16.delayed_parts[-1][i])
- for i in range(2):
- m.d.comb += out.d32[i].eq(part_32.delayed_parts[-1][i])
- m.d.comb += out.out8.eq(io8.output)
- m.d.comb += out.out16.eq(io16.output)
- m.d.comb += out.out32.eq(io32.output)
- m.d.comb += out.out64.eq(io64.output)
- m.d.comb += self.output.eq(out.output)
+ m.submodules.fo = fo = FinalOut(64)
+ for i in range(len(part_8.delayed_parts[-1])):
+ m.d.comb += fo.d8[i].eq(part_8.dplast[i])
+ for i in range(len(part_16.delayed_parts[-1])):
+ m.d.comb += fo.d16[i].eq(part_16.dplast[i])
+ for i in range(len(part_32.delayed_parts[-1])):
+ m.d.comb += fo.d32[i].eq(part_32.dplast[i])
+ m.d.comb += fo.i8.eq(io8.output)
+ m.d.comb += fo.i16.eq(io16.output)
+ m.d.comb += fo.i32.eq(io32.output)
+ m.d.comb += fo.i64.eq(io64.output)
+ m.d.comb += self.output.eq(fo.out)
return m
projects / ieee754fpu.git / blobdiff