expanded_width += 1
expanded_width += 1
self._expanded_width = expanded_width
+ # XXX these have to remain here due to some horrible nmigen
+ # simulation bugs involving sync. it is *not* necessary to
+ # have them here, they should (under normal circumstances)
+ # be moved into elaborate, as they are entirely local
self._expanded_a = Signal(expanded_width)
self._expanded_b = Signal(expanded_width)
self._expanded_output = Signal(expanded_width)
return value
-class Term(Elaboratable):
- def __init__(self, width, twidth, shift=0, enabled=None):
- self.width = width
- self.shift = shift
- self.enabled = enabled
- self.ti = Signal(width, reset_less=True)
- self.term = Signal(twidth, reset_less=True)
-
- def elaborate(self, platform):
-
- m = Module()
- m.d.comb += self.term.eq(get_term(self.ti, self.shift, self.enabled))
-
- return m
-
-
class ProductTerm(Elaboratable):
+
def __init__(self, width, twidth, pbwid, a_index, b_index):
self.a_index = a_index
self.b_index = b_index
shift = 8 * (self.a_index + self.b_index)
self.pwidth = width
+ self.twidth = twidth
+ self.width = width*2
+ self.shift = shift
+
+ self.ti = Signal(self.width, reset_less=True)
+ self.term = Signal(twidth, reset_less=True)
self.a = Signal(twidth//2, reset_less=True)
self.b = Signal(twidth//2, reset_less=True)
self.pb_en = Signal(pbwid, reset_less=True)
term_enabled = Signal(name=name, reset_less=True)
else:
term_enabled = None
-
- Term.__init__(self, width*2, twidth, shift, term_enabled)
+ self.enabled = term_enabled
self.term.name = "term_%d_%d" % (a_index, b_index) # rename
def elaborate(self, platform):
- m = Term.elaborate(self, platform)
+ m = Module()
if self.enabled is not None:
m.d.comb += self.enabled.eq(~(Cat(*self.tl).bool()))
m.d.comb += bsa.eq(self.a.bit_select(a_index * pwidth, pwidth))
m.d.comb += bsb.eq(self.b.bit_select(b_index * pwidth, pwidth))
m.d.comb += self.ti.eq(bsa * bsb)
+ m.d.comb += self.term.eq(get_term(self.ti, self.shift, self.enabled))
+ """
+ #TODO: sort out width issues, get inputs a/b switched on/off.
+ #data going into Muxes is 1/2 the required width
+
+ pwidth = self.pwidth
+ width = self.width
+ bsa = Signal(self.twidth//2, reset_less=True)
+ bsb = Signal(self.twidth//2, reset_less=True)
+ asel = Signal(width, reset_less=True)
+ bsel = Signal(width, reset_less=True)
+ a_index, b_index = self.a_index, self.b_index
+ m.d.comb += asel.eq(self.a.bit_select(a_index * pwidth, pwidth))
+ m.d.comb += bsel.eq(self.b.bit_select(b_index * pwidth, pwidth))
+ m.d.comb += bsa.eq(get_term(asel, self.shift, self.enabled))
+ m.d.comb += bsb.eq(get_term(bsel, self.shift, self.enabled))
+ m.d.comb += self.ti.eq(bsa * bsb)
+ m.d.comb += self.term.eq(self.ti)
+ """
return m
# inputs
self.a = Signal(64)
self.b = Signal(64)
- self._a_signed = [Signal(name=f"_a_signed_{i}") for i in range(8)]
- self._b_signed = [Signal(name=f"_b_signed_{i}") for i in range(8)]
+ self.a_signed = [Signal(name=f"a_signed_{i}") for i in range(8)]
+ self.b_signed = [Signal(name=f"_b_signed_{i}") for i in range(8)]
self.pbs = Signal(pbwid, reset_less=True)
# outputs
self.parts = [Signal(name=f"part_{i}") for i in range(n_parts)]
self.delayed_parts = [
- [Signal(name=f"delayed_part_8_{delay}_{i}")
+ [Signal(name=f"delayed_part_{delay}_{i}")
for i in range(n_parts)]
for delay in range(n_levels)]
+ # XXX REALLY WEIRD BUG - have to take a copy of the last delayed_parts
+ self.dplast = [Signal(name=f"dplast_{i}")
+ for i in range(n_parts)]
self.not_a_term = Signal(width)
self.neg_lsb_a_term = Signal(width)
m.d.comb += delayed_parts[0][i].eq(parts[i])
m.d.sync += [delayed_parts[j + 1][i].eq(delayed_parts[j][i])
for j in range(len(delayed_parts)-1)]
+ m.d.comb += self.dplast[i].eq(delayed_parts[-1][i])
not_a_term, neg_lsb_a_term, not_b_term, neg_lsb_b_term = \
self.not_a_term, self.neg_lsb_a_term, \
nat, nbt, nla, nlb = [], [], [], []
for i in range(len(parts)):
be = parts[i] & self.a[(i + 1) * bit_width - 1] \
- & self._a_signed[i * byte_width]
+ & self.a_signed[i * byte_width]
ae = parts[i] & self.b[(i + 1) * bit_width - 1] \
- & self._b_signed[i * byte_width]
+ & self.b_signed[i * byte_width]
a_enabled = Signal(name="a_en_%d" % i, reset_less=True)
b_enabled = Signal(name="b_en_%d" % i, reset_less=True)
m.d.comb += a_enabled.eq(ae)
w = self.width
sel = w // 8
for i in range(self.n_parts):
- op = Signal(w, reset_less=True, name="op32_%d" % i)
+ op = Signal(w, reset_less=True, name="op%d_%d" % (w, i))
m.d.comb += op.eq(
Mux(self.delayed_part_ops[sel * i] == OP_MUL_LOW,
self.intermed.bit_select(i * w*2, w),
return m
+
+class FinalOut(Elaboratable):
+ def __init__(self, out_wid):
+ # inputs
+ self.d8 = [Signal(name=f"d8_{i}", reset_less=True) for i in range(8)]
+ self.d16 = [Signal(name=f"d16_{i}", reset_less=True) for i in range(4)]
+ self.d32 = [Signal(name=f"d32_{i}", reset_less=True) for i in range(2)]
+ self.d64 = [Signal(name=f"d64_{i}", reset_less=True) for i in range(1)]
+
+ self.i8 = Signal(out_wid, reset_less=True)
+ self.i16 = Signal(out_wid, reset_less=True)
+ self.i32 = Signal(out_wid, reset_less=True)
+ self.i64 = Signal(out_wid, reset_less=True)
+
+ # output
+ self.out = Signal(out_wid, reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+ ol = []
+ for i in range(8):
+ op = Signal(8, reset_less=True, name="op_%d" % i)
+ choice = Signal(4, reset_less=True)
+ m.d.comb += choice.eq(Cat(self.d8[i], self.d16[i//2],
+ self.d32[i//4], self.d64[i//8]))
+ # select one of the outputs.
+ with m.Switch(choice):
+ with m.Case(0b0001): # d8
+ m.d.comb += op.eq(self.i8.bit_select(i * 8, 8))
+ with m.Case(0b0010): # d16
+ m.d.comb += op.eq(self.i16.bit_select(i * 8, 8))
+ with m.Case(0b0100): # d32
+ m.d.comb += op.eq(self.i32.bit_select(i * 8, 8))
+ with m.Case(0b1000): # d64
+ m.d.comb += op.eq(self.i64.bit_select(i * 8, 8))
+ ol.append(op)
+ m.d.comb += self.out.eq(Cat(*ol))
+ return m
+
+
class OrMod(Elaboratable):
def __init__(self, wid):
self.wid = wid
return m
+class Signs(Elaboratable):
+
+ def __init__(self):
+ self.part_ops = Signal(2, reset_less=True)
+ self.a_signed = Signal(reset_less=True)
+ self.b_signed = Signal(reset_less=True)
+
+ def elaborate(self, platform):
+
+ m = Module()
+
+ asig = self.part_ops != OP_MUL_UNSIGNED_HIGH
+ bsig = (self.part_ops == OP_MUL_LOW) \
+ | (self.part_ops == OP_MUL_SIGNED_HIGH)
+ m.d.comb += self.a_signed.eq(asig)
+ m.d.comb += self.b_signed.eq(bsig)
+
+ return m
+
+
class Mul8_16_32_64(Elaboratable):
"""Signed/Unsigned 8/16/32/64-bit partitioned integer multiplier.
m.d.comb += pbs.eq(Cat(*tl))
# local variables
- output_64 = Signal(64)
- output_32 = Signal(64)
- output_16 = Signal(64)
- output_8 = Signal(64)
- a_signed = [Signal(name=f"_a_signed_{i}") for i in range(8)]
- b_signed = [Signal(name=f"_b_signed_{i}") for i in range(8)]
+ signs = []
+ for i in range(8):
+ s = Signs()
+ signs.append(s)
+ setattr(m.submodules, "signs%d" % i, s)
+ m.d.comb += s.part_ops.eq(self.part_ops[i])
delayed_part_ops = [
[Signal(2, name=f"_delayed_part_ops_{delay}_{i}")
for mod in [part_8, part_16, part_32, part_64]:
m.d.comb += mod.a.eq(self.a)
m.d.comb += mod.b.eq(self.b)
- for i in range(len(a_signed)):
- m.d.comb += mod._a_signed[i].eq(a_signed[i])
- for i in range(len(b_signed)):
- m.d.comb += mod._b_signed[i].eq(b_signed[i])
+ for i in range(len(signs)):
+ m.d.comb += mod.a_signed[i].eq(signs[i].a_signed)
+ m.d.comb += mod.b_signed[i].eq(signs[i].b_signed)
m.d.comb += mod.pbs.eq(pbs)
nat_l.append(mod.not_a_term)
nbt_l.append(mod.not_b_term)
for term in t.terms:
terms.append(term)
- for i in range(8):
- asig = self.part_ops[i] != OP_MUL_UNSIGNED_HIGH
- bsig = (self.part_ops[i] == OP_MUL_LOW) \
- | (self.part_ops[i] == OP_MUL_SIGNED_HIGH)
- m.d.comb += a_signed[i].eq(asig)
- m.d.comb += b_signed[i].eq(bsig)
-
# it's fine to bitwise-or data together since they are never enabled
# at the same time
m.submodules.nat_or = nat_or = OrMod(128)
m.d.comb += io64.intermed.eq(self._intermediate_output)
for i in range(8):
m.d.comb += io64.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
- m.d.comb += output_64.eq(io64.output)
# create _output_32
m.submodules.io32 = io32 = IntermediateOut(32, 128, 2)
m.d.comb += io32.intermed.eq(self._intermediate_output)
for i in range(8):
m.d.comb += io32.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
- m.d.comb += output_32.eq(io32.output)
# create _output_16
m.submodules.io16 = io16 = IntermediateOut(16, 128, 4)
m.d.comb += io16.intermed.eq(self._intermediate_output)
for i in range(8):
m.d.comb += io16.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
- m.d.comb += output_16.eq(io16.output)
# create _output_8
m.submodules.io8 = io8 = IntermediateOut(8, 128, 8)
m.d.comb += io8.intermed.eq(self._intermediate_output)
for i in range(8):
m.d.comb += io8.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
- m.d.comb += output_8.eq(io8.output)
# final output
- ol = []
- for i in range(8):
- op = Signal(8, reset_less=True, name="op%d" % i)
- m.d.comb += op.eq(
- Mux(part_8.delayed_parts[-1][i]
- | part_16.delayed_parts[-1][i // 2],
- Mux(part_8.delayed_parts[-1][i],
- output_8.bit_select(i * 8, 8),
- output_16.bit_select(i * 8, 8)),
- Mux(part_32.delayed_parts[-1][i // 4],
- output_32.bit_select(i * 8, 8),
- output_64.bit_select(i * 8, 8))))
- ol.append(op)
- m.d.comb += self.output.eq(Cat(*ol))
+ m.submodules.fo = fo = FinalOut(64)
+ for i in range(len(part_8.delayed_parts[-1])):
+ m.d.comb += fo.d8[i].eq(part_8.dplast[i])
+ for i in range(len(part_16.delayed_parts[-1])):
+ m.d.comb += fo.d16[i].eq(part_16.dplast[i])
+ for i in range(len(part_32.delayed_parts[-1])):
+ m.d.comb += fo.d32[i].eq(part_32.dplast[i])
+ for i in range(len(part_64.delayed_parts[-1])):
+ m.d.comb += fo.d64[i].eq(part_64.dplast[i])
+ m.d.comb += fo.i8.eq(io8.output)
+ m.d.comb += fo.i16.eq(io16.output)
+ m.d.comb += fo.i32.eq(io32.output)
+ m.d.comb += fo.i64.eq(io64.output)
+ m.d.comb += self.output.eq(fo.out)
+
return m
projects / ieee754fpu.git / blobdiff