OP_MUL_UNSIGNED_HIGH = 3
+def get_term(value, shift=0, enabled=None):
+ if enabled is not None:
+ value = Mux(enabled, value, 0)
+ if shift > 0:
+ value = Cat(Repl(C(0, 1), shift), value)
+ else:
+ assert shift == 0
+ return value
+
+
+def g_add_term(m, terms, value, shift=0, enabled=None):
+ term = Signal(128, reset_less=True)
+ terms.append(term)
+ m.d.comb += term.eq(get_term(value, shift, enabled))
+
+
+class Term(Elaboratable):
+ def __init__(self, width, twidth, pbwid, a_index, b_index):
+ self.a_index = a_index
+ self.b_index = b_index
+ self.width = width
+ self.a = Signal(width, reset_less=True)
+ self.b = Signal(width, reset_less=True)
+ self.term = Signal(twidth, reset_less=True)
+ self.pb_en = Signal(pbwid, reset_less=True)
+
+ def elaborate(self, platform):
+
+ m = Module()
+ product = Signal(self.width*2, reset_less=True)
+ m.d.comb += product.eq(self.a * self.b)
+
+ tl = []
+ min_index = min(self.a_index, self.b_index)
+ max_index = max(self.a_index, self.b_index)
+ for i in range(min_index, max_index):
+ tl.append(self.pb_en[i])
+ name = "te_%d_%d" % (self.a_index, self.b_index)
+ if len(tl) > 0:
+ term_enabled = Signal(name=name, reset_less=True)
+ m.d.comb += term_enabled.eq(~(Cat(*tl).bool()))
+ else:
+ term_enabled = None
+ shift = 8 * (self.a_index + self.b_index)
+ m.d.comb += self.term.eq(get_term(product, shift, term_enabled))
+
+ return m
+
+
class Mul8_16_32_64(Elaboratable):
"""Signed/Unsigned 8/16/32/64-bit partitioned integer multiplier.
def elaborate(self, platform):
m = Module()
+ # collect part-bytes
+ pbs = Signal(8, reset_less=True)
+ tl = []
+ for i in range(8):
+ pb = Signal(name="pb%d" % i, reset_less=True)
+ m.d.comb += pb.eq(self._part_byte(i))
+ tl.append(pb)
+ m.d.comb += pbs.eq(Cat(*tl))
+
for i in range(len(self.part_ops)):
m.d.comb += self._delayed_part_ops[0][i].eq(self.part_ops[i])
m.d.sync += [self._delayed_part_ops[j + 1][i]
(self._part_8, self._delayed_part_8)]:
byte_count = 8 // len(parts)
for i in range(len(parts)):
- pb = self._part_byte(i * byte_count - 1)
+ pb = pbs[i * byte_count - 1]
value = add_intermediate_value(pb)
for j in range(i * byte_count, (i + 1) * byte_count - 1):
- pb = add_intermediate_value(~self._part_byte(j))
+ pb = add_intermediate_value(~pbs[j])
value = add_intermediate_value(value & pb)
- pb = self._part_byte((i + 1) * byte_count - 1)
+ pb = pbs[(i + 1) * byte_count - 1]
value = add_intermediate_value(value & pb)
m.d.comb += parts[i].eq(value)
m.d.comb += delayed_parts[0][i].eq(parts[i])
m.d.sync += [delayed_parts[j + 1][i].eq(delayed_parts[j][i])
for j in range(len(self.register_levels))]
- products = [[
- Signal(16, name=f"products_{i}_{j}", reset_less=True)
- for j in range(8)]
- for i in range(8)]
+ terms = []
for a_index in range(8):
for b_index in range(8):
- a = self.a.bit_select(a_index * 8, 8)
- b = self.b.bit_select(b_index * 8, 8)
- m.d.comb += products[a_index][b_index].eq(a * b)
+ t = Term(8, 128, 8, a_index, b_index)
+ setattr(m.submodules, "term_%d_%d" % (a_index, b_index), t)
- terms = []
+ m.d.comb += t.a.eq(self.a.bit_select(a_index * 8, 8))
+ m.d.comb += t.b.eq(self.b.bit_select(b_index * 8, 8))
+ m.d.comb += t.pb_en.eq(pbs)
- def add_term(value, shift=0, enabled=None):
- term = Signal(128, reset_less=True)
- terms.append(term)
- if enabled is not None:
- value = Mux(enabled, value, 0)
- if shift > 0:
- value = Cat(Repl(C(0, 1), shift), value)
- else:
- assert shift == 0
- m.d.comb += term.eq(value)
+ terms.append(t.term)
- for a_index in range(8):
- for b_index in range(8):
- tl = []
- min_index = min(a_index, b_index)
- max_index = max(a_index, b_index)
- for i in range(min_index, max_index):
- pbs = Signal(reset_less=True)
- m.d.comb += pbs.eq(self._part_byte(i))
- tl.append(pbs)
- name = "te_%d_%d" % (a_index, b_index)
- term_enabled = Signal(name=name, reset_less=True)
- m.d.comb += term_enabled.eq(~(Cat(*tl).bool()))
- add_term(products[a_index][b_index],
- 8 * (a_index + b_index),
- term_enabled)
+ def add_term(value, shift=0, enabled=None):
+ g_add_term(m, terms, value, shift, enabled)
for i in range(8):
a_signed = self.part_ops[i] != OP_MUL_UNSIGNED_HIGH
b_signed = (self.part_ops[i] == OP_MUL_LOW) \
- | (self.part_ops[i] == OP_MUL_SIGNED_HIGH)
+ | (self.part_ops[i] == OP_MUL_SIGNED_HIGH)
m.d.comb += self._a_signed[i].eq(a_signed)
m.d.comb += self._b_signed[i].eq(b_signed)
]:
byte_width = 8 // len(parts)
bit_width = 8 * byte_width
+ nat, nbt, nla, nlb = [], [], [], []
for i in range(len(parts)):
be = parts[i] & self.a[(i + 1) * bit_width - 1] \
& self._a_signed[i * byte_width]
# for 8-bit values: form a * 0xFF00 by using -a * 0x100, the
# negation operation is split into a bitwise not and a +1.
# likewise for 16, 32, and 64-bit values.
- m.d.comb += [
- not_a_term.bit_select(bit_width * 2 * i, bit_width * 2)
- .eq(Mux(a_enabled,
- Cat(Repl(0, bit_width),
- ~self.a.bit_select(bit_width * i, bit_width)),
- 0)),
-
- neg_lsb_a_term.bit_select(bit_width * 2 * i, bit_width * 2)
- .eq(Cat(Repl(0, bit_width), a_enabled)),
-
- not_b_term.bit_select(bit_width * 2 * i, bit_width * 2)
- .eq(Mux(b_enabled,
- Cat(Repl(0, bit_width),
- ~self.b.bit_select(bit_width * i, bit_width)),
- 0)),
-
- neg_lsb_b_term.bit_select(bit_width * 2 * i, bit_width * 2)
- .eq(Cat(Repl(0, bit_width), b_enabled))]
+ nat.append(Mux(a_enabled,
+ Cat(Repl(0, bit_width),
+ ~self.a.bit_select(bit_width * i, bit_width)),
+ 0))
+
+ nla.append(Cat(Repl(0, bit_width), a_enabled,
+ Repl(0, bit_width-1)))
+
+ nbt.append(Mux(b_enabled,
+ Cat(Repl(0, bit_width),
+ ~self.b.bit_select(bit_width * i, bit_width)),
+ 0))
+
+ nlb.append(Cat(Repl(0, bit_width), b_enabled,
+ Repl(0, bit_width-1)))
+
+ m.d.comb += [not_a_term.eq(Cat(*nat)),
+ not_b_term.eq(Cat(*nbt)),
+ neg_lsb_a_term.eq(Cat(*nla)),
+ neg_lsb_b_term.eq(Cat(*nlb)),
+ ]
expanded_part_pts = PartitionPoints()
for i, v in self.part_pts.items():
projects / ieee754fpu.git / blobdiff