a_enabled and b_enabled into signals

[ieee754fpu.git] / src / ieee754 / part_mul_add / multiply.py

diff --git a/src/ieee754/part_mul_add/multiply.py b/src/ieee754/part_mul_add/multiply.py
index f0bb95b5dc5cabae2e3def234f21a7391861cb85..bdbb28cc8d9ec04ab9b226dccb3a4d61934e222e 100644 (file)
--- a/src/ieee754/part_mul_add/multiply.py
+++ b/src/ieee754/part_mul_add/multiply.py
@@ -313,7 +313,6 @@ class AddReduce(Elaboratable):
                 m.d.comb += self.output.eq(adder.output)
             return m
         # go on to handle recursive case
-        intermediate_terms: List[Signal]
         intermediate_terms = []
 
         def add_intermediate_term(value):
@@ -323,7 +322,10 @@ class AddReduce(Elaboratable):
             intermediate_terms.append(intermediate_term)
             m.d.comb += intermediate_term.eq(value)
 
-        part_mask = self._reg_partition_points.as_mask(len(self.output))
+        # store mask in intermediary (simplifies graph)
+        part_mask = Signal(len(self.output), reset_less=True)
+        mask = self._reg_partition_points.as_mask(len(self.output))
+        m.d.comb += part_mask.eq(mask)
 
         # create full adders for this recursive level.
         # this shrinks N terms to 2 * (N // 3) plus the remainder
@@ -463,16 +465,24 @@ class Mul8_16_32_64(Elaboratable):
                          .eq(self._delayed_part_ops[j][i])
                          for j in range(len(self.register_levels))]
 
+        def add_intermediate_value(value):
+            intermediate_value = Signal(len(value), reset_less=True)
+            m.d.comb += intermediate_value.eq(value)
+            return intermediate_value
+
         for parts, delayed_parts in [(self._part_64, self._delayed_part_64),
                                      (self._part_32, self._delayed_part_32),
                                      (self._part_16, self._delayed_part_16),
                                      (self._part_8, self._delayed_part_8)]:
             byte_count = 8 // len(parts)
             for i in range(len(parts)):
-                value = self._part_byte(i * byte_count - 1)
+                pb = self._part_byte(i * byte_count - 1)
+                value = add_intermediate_value(pb)
                 for j in range(i * byte_count, (i + 1) * byte_count - 1):
-                    value &= ~self._part_byte(j)
-                value &= self._part_byte((i + 1) * byte_count - 1)
+                    pb = add_intermediate_value(~self._part_byte(j))
+                    value = add_intermediate_value(value & pb)
+                pb = self._part_byte((i + 1) * byte_count - 1)
+                value = add_intermediate_value(value & pb)
                 m.d.comb += parts[i].eq(value)
                 m.d.comb += delayed_parts[0][i].eq(parts[i])
                 m.d.sync += [delayed_parts[j + 1][i].eq(delayed_parts[j][i])
@@ -560,10 +570,14 @@ class Mul8_16_32_64(Elaboratable):
             byte_width = 8 // len(parts)
             bit_width = 8 * byte_width
             for i in range(len(parts)):
-                b_enabled = parts[i] & self.a[(i + 1) * bit_width - 1] \
+                ae = parts[i] & self.a[(i + 1) * bit_width - 1] \
                     & self._a_signed[i * byte_width]
-                a_enabled = parts[i] & self.b[(i + 1) * bit_width - 1] \
+                be = parts[i] & self.b[(i + 1) * bit_width - 1] \
                     & self._b_signed[i * byte_width]
+                a_enabled = Signal(name="a_enabled_%d" % i, reset_less=True)
+                b_enabled = Signal(name="b_enabled_%d" % i, reset_less=True)
+                m.d.comb += a_enabled.eq(ae)
+                m.d.comb += b_enabled.eq(be)
 
                 # for 8-bit values: form a * 0xFF00 by using -a * 0x100, the
                 # negation operation is split into a bitwise not and a +1.