whoops, a-enabled and b-enabled swapped

[ieee754fpu.git] / src / ieee754 / part_mul_add / multiply.py

diff --git a/src/ieee754/part_mul_add/multiply.py b/src/ieee754/part_mul_add/multiply.py
index 3b604bda5c1cfb68d912bae7801f214980f1a54d..dba87880e6012a3d942443cbf6b260712d5c7c75 100644 (file)
--- a/src/ieee754/part_mul_add/multiply.py
+++ b/src/ieee754/part_mul_add/multiply.py
@@ -199,7 +199,7 @@ class PartitionedAdder(Elaboratable):
         # combine above using Cat
         m.d.comb += Cat(*ea).eq(Cat(*al))
         m.d.comb += Cat(*eb).eq(Cat(*bl))
-        m.d.comb += Cat(*eo).eq(Cat(*ol))
+        m.d.comb += Cat(*ol).eq(Cat(*eo))
         # use only one addition to take advantage of look-ahead carry and
         # special hardware on FPGAs
         m.d.comb += self._expanded_output.eq(
@@ -575,12 +575,12 @@ class Mul8_16_32_64(Elaboratable):
             byte_width = 8 // len(parts)
             bit_width = 8 * byte_width
             for i in range(len(parts)):
-                ae = parts[i] & self.a[(i + 1) * bit_width - 1] \
+                be = parts[i] & self.a[(i + 1) * bit_width - 1] \
                     & self._a_signed[i * byte_width]
-                be = parts[i] & self.b[(i + 1) * bit_width - 1] \
+                ae = parts[i] & self.b[(i + 1) * bit_width - 1] \
                     & self._b_signed[i * byte_width]
-                a_enabled = Signal(name="a_enabled_%d" % i, reset_less=True)
-                b_enabled = Signal(name="b_enabled_%d" % i, reset_less=True)
+                a_enabled = Signal(name="a_en_%d" % i, reset_less=True)
+                b_enabled = Signal(name="b_en_%d" % i, reset_less=True)
                 m.d.comb += a_enabled.eq(ae)
                 m.d.comb += b_enabled.eq(be)
 
@@ -626,34 +626,41 @@ class Mul8_16_32_64(Elaboratable):
         # create _output_32
         ol = []
         for i in range(2):
-            ol.append(
+            op = Signal(32, reset_less=True, name="op32_%d" % i)
+            m.d.comb += op.eq(
                 Mux(self._delayed_part_ops[-1][4 * i] == OP_MUL_LOW,
                     self._intermediate_output.part(i * 64, 32),
                     self._intermediate_output.part(i * 64 + 32, 32)))
+            ol.append(op)
         m.d.comb += self._output_32.eq(Cat(*ol))
 
         # create _output_16
         ol = []
         for i in range(4):
-            ol.append(
+            op = Signal(16, reset_less=True, name="op16_%d" % i)
+            m.d.comb += op.eq(
                 Mux(self._delayed_part_ops[-1][2 * i] == OP_MUL_LOW,
                     self._intermediate_output.part(i * 32, 16),
                     self._intermediate_output.part(i * 32 + 16, 16)))
+            ol.append(op)
         m.d.comb += self._output_16.eq(Cat(*ol))
 
         # create _output_8
         ol = []
         for i in range(8):
-            ol.append(
+            op = Signal(8, reset_less=True, name="op8_%d" % i)
+            m.d.comb += op.eq(
                 Mux(self._delayed_part_ops[-1][i] == OP_MUL_LOW,
                     self._intermediate_output.part(i * 16, 8),
                     self._intermediate_output.part(i * 16 + 8, 8)))
+            ol.append(op)
         m.d.comb += self._output_8.eq(Cat(*ol))
 
         # final output
         ol = []
         for i in range(8):
-            ol.append(
+            op = Signal(8, reset_less=True, name="op%d" % i)
+            m.d.comb += op.eq(
                 Mux(self._delayed_part_8[-1][i]
                     | self._delayed_part_16[-1][i // 2],
                     Mux(self._delayed_part_8[-1][i],
@@ -662,6 +669,7 @@ class Mul8_16_32_64(Elaboratable):
                     Mux(self._delayed_part_32[-1][i // 4],
                         self._output_32.part(i * 8, 8),
                         self._output_64.part(i * 8, 8))))
+            ol.append(op)
         m.d.comb += self.output.eq(Cat(*ol))
         return m