# inputs
self.a = Signal(64)
self.b = Signal(64)
- self._a_signed = [Signal(name=f"_a_signed_{i}") for i in range(8)]
- self._b_signed = [Signal(name=f"_b_signed_{i}") for i in range(8)]
+ self.a_signed = [Signal(name=f"a_signed_{i}") for i in range(8)]
+ self.b_signed = [Signal(name=f"_b_signed_{i}") for i in range(8)]
self.pbs = Signal(pbwid, reset_less=True)
# outputs
nat, nbt, nla, nlb = [], [], [], []
for i in range(len(parts)):
be = parts[i] & self.a[(i + 1) * bit_width - 1] \
- & self._a_signed[i * byte_width]
+ & self.a_signed[i * byte_width]
ae = parts[i] & self.b[(i + 1) * bit_width - 1] \
- & self._b_signed[i * byte_width]
+ & self.b_signed[i * byte_width]
a_enabled = Signal(name="a_en_%d" % i, reset_less=True)
b_enabled = Signal(name="b_en_%d" % i, reset_less=True)
m.d.comb += a_enabled.eq(ae)
w = self.width
sel = w // 8
for i in range(self.n_parts):
- op = Signal(w, reset_less=True, name="op32_%d" % i)
+ op = Signal(w, reset_less=True, name="op%d_%d" % (w, i))
m.d.comb += op.eq(
Mux(self.delayed_part_ops[sel * i] == OP_MUL_LOW,
self.intermed.bit_select(i * w*2, w),
return m
+
+class FinalOut(Elaboratable):
+ def __init__(self, out_wid):
+ # inputs
+ self.d8 = [Signal(name=f"d8_{i}", reset_less=True) for i in range(8)]
+ self.d16 = [Signal(name=f"d16_{i}", reset_less=True) for i in range(4)]
+ self.d32 = [Signal(name=f"d32_{i}", reset_less=True) for i in range(2)]
+
+ self.i8 = Signal(out_wid, reset_less=True)
+ self.i16 = Signal(out_wid, reset_less=True)
+ self.i32 = Signal(out_wid, reset_less=True)
+ self.i64 = Signal(out_wid, reset_less=True)
+
+ # output
+ self.out = Signal(out_wid, reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+ ol = []
+ for i in range(8):
+ op = Signal(8, reset_less=True, name="op_%d" % i)
+ m.d.comb += op.eq(
+ Mux(self.d8[i] | self.d16[i // 2],
+ Mux(self.d8[i], self.i8.bit_select(i * 8, 8),
+ self.i16.bit_select(i * 8, 8)),
+ Mux(self.d32[i // 4], self.i32.bit_select(i * 8, 8),
+ self.i64.bit_select(i * 8, 8))))
+ ol.append(op)
+ m.d.comb += self.out.eq(Cat(*ol))
+ return m
+
+
class OrMod(Elaboratable):
def __init__(self, wid):
self.wid = wid
return m
+class Signs(Elaboratable):
+
+ def __init__(self):
+ self.part_ops = Signal(2, reset_less=True)
+ self.a_signed = Signal(reset_less=True)
+ self.b_signed = Signal(reset_less=True)
+
+ def elaborate(self, platform):
+
+ m = Module()
+
+ asig = self.part_ops != OP_MUL_UNSIGNED_HIGH
+ bsig = (self.part_ops == OP_MUL_LOW) \
+ | (self.part_ops == OP_MUL_SIGNED_HIGH)
+ m.d.comb += self.a_signed.eq(asig)
+ m.d.comb += self.b_signed.eq(bsig)
+
+ return m
+
+
class Mul8_16_32_64(Elaboratable):
"""Signed/Unsigned 8/16/32/64-bit partitioned integer multiplier.
m.d.comb += pbs.eq(Cat(*tl))
# local variables
- output_64 = Signal(64)
- output_32 = Signal(64)
- output_16 = Signal(64)
- output_8 = Signal(64)
- a_signed = [Signal(name=f"_a_signed_{i}") for i in range(8)]
- b_signed = [Signal(name=f"_b_signed_{i}") for i in range(8)]
+ signs = []
+ for i in range(8):
+ s = Signs()
+ signs.append(s)
+ setattr(m.submodules, "signs%d" % i, s)
+ m.d.comb += s.part_ops.eq(self.part_ops[i])
delayed_part_ops = [
[Signal(2, name=f"_delayed_part_ops_{delay}_{i}")
for mod in [part_8, part_16, part_32, part_64]:
m.d.comb += mod.a.eq(self.a)
m.d.comb += mod.b.eq(self.b)
- for i in range(len(a_signed)):
- m.d.comb += mod._a_signed[i].eq(a_signed[i])
- for i in range(len(b_signed)):
- m.d.comb += mod._b_signed[i].eq(b_signed[i])
+ for i in range(len(signs)):
+ m.d.comb += mod.a_signed[i].eq(signs[i].a_signed)
+ m.d.comb += mod.b_signed[i].eq(signs[i].b_signed)
m.d.comb += mod.pbs.eq(pbs)
nat_l.append(mod.not_a_term)
nbt_l.append(mod.not_b_term)
for term in t.terms:
terms.append(term)
- for i in range(8):
- asig = self.part_ops[i] != OP_MUL_UNSIGNED_HIGH
- bsig = (self.part_ops[i] == OP_MUL_LOW) \
- | (self.part_ops[i] == OP_MUL_SIGNED_HIGH)
- m.d.comb += a_signed[i].eq(asig)
- m.d.comb += b_signed[i].eq(bsig)
-
# it's fine to bitwise-or data together since they are never enabled
# at the same time
m.submodules.nat_or = nat_or = OrMod(128)
m.d.comb += io64.intermed.eq(self._intermediate_output)
for i in range(8):
m.d.comb += io64.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
- m.d.comb += output_64.eq(io64.output)
# create _output_32
m.submodules.io32 = io32 = IntermediateOut(32, 128, 2)
m.d.comb += io32.intermed.eq(self._intermediate_output)
for i in range(8):
m.d.comb += io32.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
- m.d.comb += output_32.eq(io32.output)
# create _output_16
m.submodules.io16 = io16 = IntermediateOut(16, 128, 4)
m.d.comb += io16.intermed.eq(self._intermediate_output)
for i in range(8):
m.d.comb += io16.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
- m.d.comb += output_16.eq(io16.output)
# create _output_8
m.submodules.io8 = io8 = IntermediateOut(8, 128, 8)
m.d.comb += io8.intermed.eq(self._intermediate_output)
for i in range(8):
m.d.comb += io8.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
- m.d.comb += output_8.eq(io8.output)
# final output
- ol = []
+ m.submodules.fo = fo = FinalOut(64)
for i in range(8):
- op = Signal(8, reset_less=True, name="op%d" % i)
- m.d.comb += op.eq(
- Mux(part_8.delayed_parts[-1][i]
- | part_16.delayed_parts[-1][i // 2],
- Mux(part_8.delayed_parts[-1][i],
- output_8.bit_select(i * 8, 8),
- output_16.bit_select(i * 8, 8)),
- Mux(part_32.delayed_parts[-1][i // 4],
- output_32.bit_select(i * 8, 8),
- output_64.bit_select(i * 8, 8))))
- ol.append(op)
- m.d.comb += self.output.eq(Cat(*ol))
+ m.d.comb += fo.d8[i].eq(part_8.delayed_parts[-1][i])
+ for i in range(4):
+ m.d.comb += fo.d16[i].eq(part_16.delayed_parts[-1][i])
+ for i in range(2):
+ m.d.comb += fo.d32[i].eq(part_32.delayed_parts[-1][i])
+ m.d.comb += fo.i8.eq(io8.output)
+ m.d.comb += fo.i16.eq(io16.output)
+ m.d.comb += fo.i32.eq(io32.output)
+ m.d.comb += fo.i64.eq(io64.output)
+ m.d.comb += self.output.eq(fo.out)
+
return m
projects / ieee754fpu.git / blobdiff