from nmigen.hdl.ast import Assign
from abc import ABCMeta, abstractmethod
from nmigen.cli import main
-
+from functools import reduce
+from operator import or_
class PartitionPoints(dict):
"""Partition points and corresponding ``Value``s.
OP_MUL_UNSIGNED_HIGH = 3
+def get_term(value, shift=0, enabled=None):
+ if enabled is not None:
+ value = Mux(enabled, value, 0)
+ if shift > 0:
+ value = Cat(Repl(C(0, 1), shift), value)
+ else:
+ assert shift == 0
+ return value
+
+
+class Term(Elaboratable):
+ def __init__(self, width, twidth, shift=0, enabled=None):
+ self.width = width
+ self.shift = shift
+ self.enabled = enabled
+ self.ti = Signal(width, reset_less=True)
+ self.term = Signal(twidth, reset_less=True)
+
+ def elaborate(self, platform):
+
+ m = Module()
+ m.d.comb += self.term.eq(get_term(self.ti, self.shift, self.enabled))
+
+ return m
+
+
+class ProductTerm(Elaboratable):
+ def __init__(self, width, twidth, pbwid, a_index, b_index):
+ self.a_index = a_index
+ self.b_index = b_index
+ shift = 8 * (self.a_index + self.b_index)
+ self.pwidth = width
+ self.a = Signal(twidth//2, reset_less=True)
+ self.b = Signal(twidth//2, reset_less=True)
+ self.pb_en = Signal(pbwid, reset_less=True)
+
+ self.tl = tl = []
+ min_index = min(self.a_index, self.b_index)
+ max_index = max(self.a_index, self.b_index)
+ for i in range(min_index, max_index):
+ tl.append(self.pb_en[i])
+ name = "te_%d_%d" % (self.a_index, self.b_index)
+ if len(tl) > 0:
+ term_enabled = Signal(name=name, reset_less=True)
+ else:
+ term_enabled = None
+
+ Term.__init__(self, width*2, twidth, shift, term_enabled)
+ self.term.name = "term_%d_%d" % (a_index, b_index) # rename
+
+ def elaborate(self, platform):
+
+ m = Term.elaborate(self, platform)
+ if self.enabled is not None:
+ m.d.comb += self.enabled.eq(~(Cat(*self.tl).bool()))
+
+ bsa = Signal(self.width, reset_less=True)
+ bsb = Signal(self.width, reset_less=True)
+ a_index, b_index = self.a_index, self.b_index
+ pwidth = self.pwidth
+ m.d.comb += bsa.eq(self.a.bit_select(a_index * pwidth, pwidth))
+ m.d.comb += bsb.eq(self.b.bit_select(b_index * pwidth, pwidth))
+ m.d.comb += self.ti.eq(bsa * bsb)
+
+ return m
+
+
+class ProductTerms(Elaboratable):
+
+ def __init__(self, width, twidth, pbwid, a_index, blen):
+ self.a_index = a_index
+ self.blen = blen
+ self.pwidth = width
+ self.twidth = twidth
+ self.pbwid = pbwid
+ self.a = Signal(twidth//2, reset_less=True)
+ self.b = Signal(twidth//2, reset_less=True)
+ self.pb_en = Signal(pbwid, reset_less=True)
+ self.terms = [Signal(twidth, name="term%d"%i, reset_less=True) \
+ for i in range(blen)]
+
+ def elaborate(self, platform):
+
+ m = Module()
+
+ for b_index in range(self.blen):
+ t = ProductTerm(self.pwidth, self.twidth, self.pbwid,
+ self.a_index, b_index)
+ setattr(m.submodules, "term_%d" % b_index, t)
+
+ m.d.comb += t.a.eq(self.a)
+ m.d.comb += t.b.eq(self.b)
+ m.d.comb += t.pb_en.eq(self.pb_en)
+
+ m.d.comb += self.terms[b_index].eq(t.term)
+
+ return m
+
+
+class Part(Elaboratable):
+ def __init__(self, width, n_parts, n_levels, pbwid):
+
+ # inputs
+ self.a = Signal(64)
+ self.b = Signal(64)
+ self.a_signed = [Signal(name=f"a_signed_{i}") for i in range(8)]
+ self.b_signed = [Signal(name=f"_b_signed_{i}") for i in range(8)]
+ self.pbs = Signal(pbwid, reset_less=True)
+
+ # outputs
+ self.parts = [Signal(name=f"part_{i}") for i in range(n_parts)]
+ self.delayed_parts = [
+ [Signal(name=f"delayed_part_8_{delay}_{i}")
+ for i in range(n_parts)]
+ for delay in range(n_levels)]
+
+ self.not_a_term = Signal(width)
+ self.neg_lsb_a_term = Signal(width)
+ self.not_b_term = Signal(width)
+ self.neg_lsb_b_term = Signal(width)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ pbs, parts, delayed_parts = self.pbs, self.parts, self.delayed_parts
+ byte_count = 8 // len(parts)
+ for i in range(len(parts)):
+ pbl = []
+ pbl.append(~pbs[i * byte_count - 1])
+ for j in range(i * byte_count, (i + 1) * byte_count - 1):
+ pbl.append(pbs[j])
+ pbl.append(~pbs[(i + 1) * byte_count - 1])
+ value = Signal(len(pbl), reset_less=True)
+ m.d.comb += value.eq(Cat(*pbl))
+ m.d.comb += parts[i].eq(~(value).bool())
+ m.d.comb += delayed_parts[0][i].eq(parts[i])
+ m.d.sync += [delayed_parts[j + 1][i].eq(delayed_parts[j][i])
+ for j in range(len(delayed_parts)-1)]
+
+ not_a_term, neg_lsb_a_term, not_b_term, neg_lsb_b_term = \
+ self.not_a_term, self.neg_lsb_a_term, \
+ self.not_b_term, self.neg_lsb_b_term
+
+ byte_width = 8 // len(parts)
+ bit_width = 8 * byte_width
+ nat, nbt, nla, nlb = [], [], [], []
+ for i in range(len(parts)):
+ be = parts[i] & self.a[(i + 1) * bit_width - 1] \
+ & self.a_signed[i * byte_width]
+ ae = parts[i] & self.b[(i + 1) * bit_width - 1] \
+ & self.b_signed[i * byte_width]
+ a_enabled = Signal(name="a_en_%d" % i, reset_less=True)
+ b_enabled = Signal(name="b_en_%d" % i, reset_less=True)
+ m.d.comb += a_enabled.eq(ae)
+ m.d.comb += b_enabled.eq(be)
+
+ # for 8-bit values: form a * 0xFF00 by using -a * 0x100, the
+ # negation operation is split into a bitwise not and a +1.
+ # likewise for 16, 32, and 64-bit values.
+ nat.append(Mux(a_enabled,
+ Cat(Repl(0, bit_width),
+ ~self.a.bit_select(bit_width * i, bit_width)),
+ 0))
+
+ nla.append(Cat(Repl(0, bit_width), a_enabled,
+ Repl(0, bit_width-1)))
+
+ nbt.append(Mux(b_enabled,
+ Cat(Repl(0, bit_width),
+ ~self.b.bit_select(bit_width * i, bit_width)),
+ 0))
+
+ nlb.append(Cat(Repl(0, bit_width), b_enabled,
+ Repl(0, bit_width-1)))
+
+ m.d.comb += [not_a_term.eq(Cat(*nat)),
+ not_b_term.eq(Cat(*nbt)),
+ neg_lsb_a_term.eq(Cat(*nla)),
+ neg_lsb_b_term.eq(Cat(*nlb)),
+ ]
+
+ return m
+
+
+class IntermediateOut(Elaboratable):
+ def __init__(self, width, out_wid, n_parts):
+ self.width = width
+ self.n_parts = n_parts
+ self.delayed_part_ops = [Signal(2, name="dpop%d" % i, reset_less=True)
+ for i in range(8)]
+ self.intermed = Signal(out_wid, reset_less=True)
+ self.output = Signal(out_wid//2, reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ ol = []
+ w = self.width
+ sel = w // 8
+ for i in range(self.n_parts):
+ op = Signal(w, reset_less=True, name="op%d_%d" % (w, i))
+ m.d.comb += op.eq(
+ Mux(self.delayed_part_ops[sel * i] == OP_MUL_LOW,
+ self.intermed.bit_select(i * w*2, w),
+ self.intermed.bit_select(i * w*2 + w, w)))
+ ol.append(op)
+ m.d.comb += self.output.eq(Cat(*ol))
+
+ return m
+
+
+class FinalOut(Elaboratable):
+ def __init__(self, out_wid):
+ # inputs
+ self.d8 = [Signal(name=f"d8_{i}", reset_less=True) for i in range(8)]
+ self.d16 = [Signal(name=f"d16_{i}", reset_less=True) for i in range(4)]
+ self.d32 = [Signal(name=f"d32_{i}", reset_less=True) for i in range(2)]
+
+ self.i8 = Signal(out_wid, reset_less=True)
+ self.i16 = Signal(out_wid, reset_less=True)
+ self.i32 = Signal(out_wid, reset_less=True)
+ self.i64 = Signal(out_wid, reset_less=True)
+
+ # output
+ self.out = Signal(out_wid, reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+ ol = []
+ for i in range(8):
+ op = Signal(8, reset_less=True, name="op_%d" % i)
+ m.d.comb += op.eq(
+ Mux(self.d8[i] | self.d16[i // 2],
+ Mux(self.d8[i], self.i8.bit_select(i * 8, 8),
+ self.i16.bit_select(i * 8, 8)),
+ Mux(self.d32[i // 4], self.i32.bit_select(i * 8, 8),
+ self.i64.bit_select(i * 8, 8))))
+ ol.append(op)
+ m.d.comb += self.out.eq(Cat(*ol))
+ return m
+
+
+class OrMod(Elaboratable):
+ def __init__(self, wid):
+ self.wid = wid
+ self.orin = [Signal(wid, name="orin%d" % i, reset_less=True)
+ for i in range(4)]
+ self.orout = Signal(wid, reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+ or1 = Signal(self.wid, reset_less=True)
+ or2 = Signal(self.wid, reset_less=True)
+ m.d.comb += or1.eq(self.orin[0] | self.orin[1])
+ m.d.comb += or2.eq(self.orin[2] | self.orin[3])
+ m.d.comb += self.orout.eq(or1 | or2)
+
+ return m
+
+
+class Signs(Elaboratable):
+
+ def __init__(self):
+ self.part_ops = Signal(2, reset_less=True)
+ self.a_signed = Signal(reset_less=True)
+ self.b_signed = Signal(reset_less=True)
+
+ def elaborate(self, platform):
+
+ m = Module()
+
+ asig = self.part_ops != OP_MUL_UNSIGNED_HIGH
+ bsig = (self.part_ops == OP_MUL_LOW) \
+ | (self.part_ops == OP_MUL_SIGNED_HIGH)
+ m.d.comb += self.a_signed.eq(asig)
+ m.d.comb += self.b_signed.eq(bsig)
+
+ return m
+
+
class Mul8_16_32_64(Elaboratable):
"""Signed/Unsigned 8/16/32/64-bit partitioned integer multiplier.
"""
def __init__(self, register_levels= ()):
+
+ # parameter(s)
+ self.register_levels = list(register_levels)
+
+ # inputs
self.part_pts = PartitionPoints()
for i in range(8, 64, 8):
self.part_pts[i] = Signal(name=f"part_pts_{i}")
self.part_ops = [Signal(2, name=f"part_ops_{i}") for i in range(8)]
self.a = Signal(64)
self.b = Signal(64)
- self.output = Signal(64)
- self.register_levels = list(register_levels)
+
+ # intermediates (needed for unit tests)
self._intermediate_output = Signal(128)
- self._delayed_part_ops = [
- [Signal(2, name=f"_delayed_part_ops_{delay}_{i}")
- for i in range(8)]
- for delay in range(1 + len(self.register_levels))]
- self._part_8 = [Signal(name=f"_part_8_{i}") for i in range(8)]
- self._part_16 = [Signal(name=f"_part_16_{i}") for i in range(4)]
- self._part_32 = [Signal(name=f"_part_32_{i}") for i in range(2)]
- self._part_64 = [Signal(name=f"_part_64")]
- self._delayed_part_8 = [
- [Signal(name=f"_delayed_part_8_{delay}_{i}")
- for i in range(8)]
- for delay in range(1 + len(self.register_levels))]
- self._delayed_part_16 = [
- [Signal(name=f"_delayed_part_16_{delay}_{i}")
- for i in range(4)]
- for delay in range(1 + len(self.register_levels))]
- self._delayed_part_32 = [
- [Signal(name=f"_delayed_part_32_{delay}_{i}")
- for i in range(2)]
- for delay in range(1 + len(self.register_levels))]
- self._delayed_part_64 = [
- [Signal(name=f"_delayed_part_64_{delay}")]
- for delay in range(1 + len(self.register_levels))]
- self._output_64 = Signal(64)
- self._output_32 = Signal(64)
- self._output_16 = Signal(64)
- self._output_8 = Signal(64)
- self._a_signed = [Signal(name=f"_a_signed_{i}") for i in range(8)]
- self._b_signed = [Signal(name=f"_b_signed_{i}") for i in range(8)]
- self._not_a_term_8 = Signal(128)
- self._neg_lsb_a_term_8 = Signal(128)
- self._not_b_term_8 = Signal(128)
- self._neg_lsb_b_term_8 = Signal(128)
- self._not_a_term_16 = Signal(128)
- self._neg_lsb_a_term_16 = Signal(128)
- self._not_b_term_16 = Signal(128)
- self._neg_lsb_b_term_16 = Signal(128)
- self._not_a_term_32 = Signal(128)
- self._neg_lsb_a_term_32 = Signal(128)
- self._not_b_term_32 = Signal(128)
- self._neg_lsb_b_term_32 = Signal(128)
- self._not_a_term_64 = Signal(128)
- self._neg_lsb_a_term_64 = Signal(128)
- self._not_b_term_64 = Signal(128)
- self._neg_lsb_b_term_64 = Signal(128)
+
+ # output
+ self.output = Signal(64)
def _part_byte(self, index):
if index == -1 or index == 7:
def elaborate(self, platform):
m = Module()
+ # collect part-bytes
+ pbs = Signal(8, reset_less=True)
+ tl = []
+ for i in range(8):
+ pb = Signal(name="pb%d" % i, reset_less=True)
+ m.d.comb += pb.eq(self._part_byte(i))
+ tl.append(pb)
+ m.d.comb += pbs.eq(Cat(*tl))
+
+ # local variables
+ signs = []
+ for i in range(8):
+ s = Signs()
+ signs.append(s)
+ setattr(m.submodules, "signs%d" % i, s)
+ m.d.comb += s.part_ops.eq(self.part_ops[i])
+
+ delayed_part_ops = [
+ [Signal(2, name=f"_delayed_part_ops_{delay}_{i}")
+ for i in range(8)]
+ for delay in range(1 + len(self.register_levels))]
for i in range(len(self.part_ops)):
- m.d.comb += self._delayed_part_ops[0][i].eq(self.part_ops[i])
- m.d.sync += [self._delayed_part_ops[j + 1][i]
- .eq(self._delayed_part_ops[j][i])
+ m.d.comb += delayed_part_ops[0][i].eq(self.part_ops[i])
+ m.d.sync += [delayed_part_ops[j + 1][i].eq(delayed_part_ops[j][i])
for j in range(len(self.register_levels))]
- def add_intermediate_value(value):
- intermediate_value = Signal(len(value), reset_less=True)
- m.d.comb += intermediate_value.eq(value)
- return intermediate_value
-
- for parts, delayed_parts in [(self._part_64, self._delayed_part_64),
- (self._part_32, self._delayed_part_32),
- (self._part_16, self._delayed_part_16),
- (self._part_8, self._delayed_part_8)]:
- byte_count = 8 // len(parts)
- for i in range(len(parts)):
- pb = self._part_byte(i * byte_count - 1)
- value = add_intermediate_value(pb)
- for j in range(i * byte_count, (i + 1) * byte_count - 1):
- pb = add_intermediate_value(~self._part_byte(j))
- value = add_intermediate_value(value & pb)
- pb = self._part_byte((i + 1) * byte_count - 1)
- value = add_intermediate_value(value & pb)
- m.d.comb += parts[i].eq(value)
- m.d.comb += delayed_parts[0][i].eq(parts[i])
- m.d.sync += [delayed_parts[j + 1][i].eq(delayed_parts[j][i])
- for j in range(len(self.register_levels))]
-
- products = [[
- Signal(16, name=f"products_{i}_{j}", reset_less=True)
- for j in range(8)]
- for i in range(8)]
-
- for a_index in range(8):
- for b_index in range(8):
- a = self.a.part(a_index * 8, 8)
- b = self.b.part(b_index * 8, 8)
- m.d.comb += products[a_index][b_index].eq(a * b)
+ n_levels = len(self.register_levels)+1
+ m.submodules.part_8 = part_8 = Part(128, 8, n_levels, 8)
+ m.submodules.part_16 = part_16 = Part(128, 4, n_levels, 8)
+ m.submodules.part_32 = part_32 = Part(128, 2, n_levels, 8)
+ m.submodules.part_64 = part_64 = Part(128, 1, n_levels, 8)
+ nat_l, nbt_l, nla_l, nlb_l = [], [], [], []
+ for mod in [part_8, part_16, part_32, part_64]:
+ m.d.comb += mod.a.eq(self.a)
+ m.d.comb += mod.b.eq(self.b)
+ for i in range(len(signs)):
+ m.d.comb += mod.a_signed[i].eq(signs[i].a_signed)
+ m.d.comb += mod.b_signed[i].eq(signs[i].b_signed)
+ m.d.comb += mod.pbs.eq(pbs)
+ nat_l.append(mod.not_a_term)
+ nbt_l.append(mod.not_b_term)
+ nla_l.append(mod.neg_lsb_a_term)
+ nlb_l.append(mod.neg_lsb_b_term)
terms = []
- def add_term(value, shift=0, enabled=None):
- term = Signal(128, reset_less=True)
- terms.append(term)
- if enabled is not None:
- value = Mux(enabled, value, 0)
- if shift > 0:
- value = Cat(Repl(C(0, 1), shift), value)
- else:
- assert shift == 0
- m.d.comb += term.eq(value)
-
for a_index in range(8):
- for b_index in range(8):
- tl = []
- min_index = min(a_index, b_index)
- max_index = max(a_index, b_index)
- for i in range(min_index, max_index):
- pbs = Signal(reset_less=True)
- m.d.comb += pbs.eq(self._part_byte(i))
- tl.append(pbs)
- name = "te_%d_%d" % (a_index, b_index)
- term_enabled = Signal(name=name, reset_less=True)
- m.d.comb += term_enabled.eq(~(Cat(*tl).bool()))
- add_term(products[a_index][b_index],
- 8 * (a_index + b_index),
- term_enabled)
+ t = ProductTerms(8, 128, 8, a_index, 8)
+ setattr(m.submodules, "terms_%d" % a_index, t)
- for i in range(8):
- a_signed = self.part_ops[i] != OP_MUL_UNSIGNED_HIGH
- b_signed = (self.part_ops[i] == OP_MUL_LOW) \
- | (self.part_ops[i] == OP_MUL_SIGNED_HIGH)
- m.d.comb += self._a_signed[i].eq(a_signed)
- m.d.comb += self._b_signed[i].eq(b_signed)
+ m.d.comb += t.a.eq(self.a)
+ m.d.comb += t.b.eq(self.b)
+ m.d.comb += t.pb_en.eq(pbs)
+
+ for term in t.terms:
+ terms.append(term)
- # it's fine to bitwise-or these together since they are never enabled
+ # it's fine to bitwise-or data together since they are never enabled
# at the same time
- add_term(self._not_a_term_8 | self._not_a_term_16
- | self._not_a_term_32 | self._not_a_term_64)
- add_term(self._neg_lsb_a_term_8 | self._neg_lsb_a_term_16
- | self._neg_lsb_a_term_32 | self._neg_lsb_a_term_64)
- add_term(self._not_b_term_8 | self._not_b_term_16
- | self._not_b_term_32 | self._not_b_term_64)
- add_term(self._neg_lsb_b_term_8 | self._neg_lsb_b_term_16
- | self._neg_lsb_b_term_32 | self._neg_lsb_b_term_64)
-
- for not_a_term, \
- neg_lsb_a_term, \
- not_b_term, \
- neg_lsb_b_term, \
- parts in [
- (self._not_a_term_8,
- self._neg_lsb_a_term_8,
- self._not_b_term_8,
- self._neg_lsb_b_term_8,
- self._part_8),
- (self._not_a_term_16,
- self._neg_lsb_a_term_16,
- self._not_b_term_16,
- self._neg_lsb_b_term_16,
- self._part_16),
- (self._not_a_term_32,
- self._neg_lsb_a_term_32,
- self._not_b_term_32,
- self._neg_lsb_b_term_32,
- self._part_32),
- (self._not_a_term_64,
- self._neg_lsb_a_term_64,
- self._not_b_term_64,
- self._neg_lsb_b_term_64,
- self._part_64),
- ]:
- byte_width = 8 // len(parts)
- bit_width = 8 * byte_width
- for i in range(len(parts)):
- ae = parts[i] & self.a[(i + 1) * bit_width - 1] \
- & self._a_signed[i * byte_width]
- be = parts[i] & self.b[(i + 1) * bit_width - 1] \
- & self._b_signed[i * byte_width]
- a_enabled = Signal(name="a_enabled_%d" % i, reset_less=True)
- b_enabled = Signal(name="b_enabled_%d" % i, reset_less=True)
- m.d.comb += a_enabled.eq(ae)
- m.d.comb += b_enabled.eq(be)
-
- # for 8-bit values: form a * 0xFF00 by using -a * 0x100, the
- # negation operation is split into a bitwise not and a +1.
- # likewise for 16, 32, and 64-bit values.
- m.d.comb += [
- not_a_term.part(bit_width * 2 * i, bit_width * 2)
- .eq(Mux(a_enabled,
- Cat(Repl(0, bit_width),
- ~self.a.part(bit_width * i, bit_width)),
- 0)),
-
- neg_lsb_a_term.part(bit_width * 2 * i, bit_width * 2)
- .eq(Cat(Repl(0, bit_width), a_enabled)),
-
- not_b_term.part(bit_width * 2 * i, bit_width * 2)
- .eq(Mux(b_enabled,
- Cat(Repl(0, bit_width),
- ~self.b.part(bit_width * i, bit_width)),
- 0)),
-
- neg_lsb_b_term.part(bit_width * 2 * i, bit_width * 2)
- .eq(Cat(Repl(0, bit_width), b_enabled))]
+ m.submodules.nat_or = nat_or = OrMod(128)
+ m.submodules.nbt_or = nbt_or = OrMod(128)
+ m.submodules.nla_or = nla_or = OrMod(128)
+ m.submodules.nlb_or = nlb_or = OrMod(128)
+ for l, mod in [(nat_l, nat_or),
+ (nbt_l, nbt_or),
+ (nla_l, nla_or),
+ (nlb_l, nlb_or)]:
+ for i in range(len(l)):
+ m.d.comb += mod.orin[i].eq(l[i])
+ terms.append(mod.orout)
expanded_part_pts = PartitionPoints()
for i, v in self.part_pts.items():
expanded_part_pts)
m.submodules.add_reduce = add_reduce
m.d.comb += self._intermediate_output.eq(add_reduce.output)
- m.d.comb += self._output_64.eq(
- Mux(self._delayed_part_ops[-1][0] == OP_MUL_LOW,
- self._intermediate_output.part(0, 64),
- self._intermediate_output.part(64, 64)))
+ # create _output_64
+ m.submodules.io64 = io64 = IntermediateOut(64, 128, 1)
+ m.d.comb += io64.intermed.eq(self._intermediate_output)
+ for i in range(8):
+ m.d.comb += io64.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
# create _output_32
- ol = []
- for i in range(2):
- ol.append(
- Mux(self._delayed_part_ops[-1][4 * i] == OP_MUL_LOW,
- self._intermediate_output.part(i * 64, 32),
- self._intermediate_output.part(i * 64 + 32, 32)))
- m.d.comb += self._output_32.eq(Cat(*ol))
+ m.submodules.io32 = io32 = IntermediateOut(32, 128, 2)
+ m.d.comb += io32.intermed.eq(self._intermediate_output)
+ for i in range(8):
+ m.d.comb += io32.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
# create _output_16
- ol = []
- for i in range(4):
- ol.append(
- Mux(self._delayed_part_ops[-1][2 * i] == OP_MUL_LOW,
- self._intermediate_output.part(i * 32, 16),
- self._intermediate_output.part(i * 32 + 16, 16)))
- m.d.comb += self._output_16.eq(Cat(*ol))
+ m.submodules.io16 = io16 = IntermediateOut(16, 128, 4)
+ m.d.comb += io16.intermed.eq(self._intermediate_output)
+ for i in range(8):
+ m.d.comb += io16.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
# create _output_8
- ol = []
+ m.submodules.io8 = io8 = IntermediateOut(8, 128, 8)
+ m.d.comb += io8.intermed.eq(self._intermediate_output)
for i in range(8):
- ol.append(
- Mux(self._delayed_part_ops[-1][i] == OP_MUL_LOW,
- self._intermediate_output.part(i * 16, 8),
- self._intermediate_output.part(i * 16 + 8, 8)))
- m.d.comb += self._output_8.eq(Cat(*ol))
+ m.d.comb += io8.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
# final output
- ol = []
+ m.submodules.fo = fo = FinalOut(64)
for i in range(8):
- ol.append(
- Mux(self._delayed_part_8[-1][i]
- | self._delayed_part_16[-1][i // 2],
- Mux(self._delayed_part_8[-1][i],
- self._output_8.part(i * 8, 8),
- self._output_16.part(i * 8, 8)),
- Mux(self._delayed_part_32[-1][i // 4],
- self._output_32.part(i * 8, 8),
- self._output_64.part(i * 8, 8))))
- m.d.comb += self.output.eq(Cat(*ol))
+ m.d.comb += fo.d8[i].eq(part_8.delayed_parts[-1][i])
+ for i in range(4):
+ m.d.comb += fo.d16[i].eq(part_16.delayed_parts[-1][i])
+ for i in range(2):
+ m.d.comb += fo.d32[i].eq(part_32.delayed_parts[-1][i])
+ m.d.comb += fo.i8.eq(io8.output)
+ m.d.comb += fo.i16.eq(io16.output)
+ m.d.comb += fo.i32.eq(io32.output)
+ m.d.comb += fo.i64.eq(io64.output)
+ m.d.comb += self.output.eq(fo.out)
+
return m
projects / ieee754fpu.git / blobdiff