from nmigen import Signal, Module, Value, Elaboratable, Cat, C, Mux, Repl
from nmigen.hdl.ast import Assign
from abc import ABCMeta, abstractmethod
-from typing import Any, NewType, Union, List, Dict, Iterable, Mapping, Optional
-from typing_extensions import final
from nmigen.cli import main
+from functools import reduce
+from operator import or_
-PartitionPointsIn = Mapping[int, Union[Value, bool, int]]
-
-
-class PartitionPoints(Dict[int, Value]):
+class PartitionPoints(dict):
"""Partition points and corresponding ``Value``s.
The points at where an ALU is partitioned along with ``Value``s that
* bits 10 <= ``i`` < 16
"""
- def __init__(self, partition_points: Optional[PartitionPointsIn] = None):
+ def __init__(self, partition_points=None):
"""Create a new ``PartitionPoints``.
:param partition_points: the input partition points to values mapping.
raise ValueError("point must be a non-negative integer")
self[point] = Value.wrap(enabled)
- def like(self,
- name: Optional[str] = None,
- src_loc_at: int = 0) -> 'PartitionPoints':
+ def like(self, name=None, src_loc_at=0):
"""Create a new ``PartitionPoints`` with ``Signal``s for all values.
:param name: the base name for the new ``Signal``s.
retval[point] = Signal(enabled.shape(), name=f"{name}_{point}")
return retval
- def eq(self, rhs: 'PartitionPoints') -> Iterable[Assign]:
+ def eq(self, rhs):
"""Assign ``PartitionPoints`` using ``Signal.eq``."""
if set(self.keys()) != set(rhs.keys()):
raise ValueError("incompatible point set")
for point, enabled in self.items():
yield enabled.eq(rhs[point])
- def as_mask(self, width: int) -> Value:
+ def as_mask(self, width):
"""Create a bit-mask from `self`.
Each bit in the returned mask is clear only if the partition point at
:param width: the bit width of the resulting mask
"""
- bits: List[Union[Value, bool]]
bits = []
for i in range(width):
if i in self:
bits.append(True)
return Cat(*bits)
- def get_max_partition_count(self, width: int) -> int:
+ def get_max_partition_count(self, width):
"""Get the maximum number of partitions.
Gets the number of partitions when all partition points are enabled.
retval += 1
return retval
- def fits_in_width(self, width: int) -> bool:
+ def fits_in_width(self, width):
"""Check if all partition points are smaller than `width`."""
for point in self.keys():
if point >= width:
return True
-@final
class FullAdder(Elaboratable):
"""Full Adder.
:attribute carry: the carry output
"""
- def __init__(self, width: int):
+ def __init__(self, width):
"""Create a ``FullAdder``.
:param width: the bit width of the input and output
self.sum = Signal(width)
self.carry = Signal(width)
- def elaborate(self, platform: Any) -> Module:
+ def elaborate(self, platform):
"""Elaborate this module."""
m = Module()
m.d.comb += self.sum.eq(self.in0 ^ self.in1 ^ self.in2)
return m
-@final
class PartitionedAdder(Elaboratable):
"""Partitioned Adder.
supported, except for by ``Signal.eq``.
"""
- def __init__(self, width: int, partition_points: PartitionPointsIn):
+ def __init__(self, width, partition_points):
"""Create a ``PartitionedAdder``.
:param width: the bit width of the input and output
self._expanded_b = Signal(expanded_width)
self._expanded_output = Signal(expanded_width)
- def elaborate(self, platform: Any) -> Module:
+ def elaborate(self, platform):
"""Elaborate this module."""
m = Module()
expanded_index = 0
+ # store bits in a list, use Cat later. graphviz is much cleaner
+ al = []
+ bl = []
+ ol = []
+ ea = []
+ eb = []
+ eo = []
+ # partition points are "breaks" (extra zeros) in what would otherwise
+ # be a massive long add.
for i in range(self.width):
if i in self.partition_points:
# add extra bit set to 0 + 0 for enabled partition points
# and 1 + 0 for disabled partition points
- m.d.comb += self._expanded_a[expanded_index].eq(
- ~self.partition_points[i])
- m.d.comb += self._expanded_b[expanded_index].eq(0)
+ ea.append(self._expanded_a[expanded_index])
+ al.append(~self.partition_points[i])
+ eb.append(self._expanded_b[expanded_index])
+ bl.append(C(0))
expanded_index += 1
- m.d.comb += self._expanded_a[expanded_index].eq(self.a[i])
- m.d.comb += self._expanded_b[expanded_index].eq(self.b[i])
- m.d.comb += self.output[i].eq(
- self._expanded_output[expanded_index])
+ ea.append(self._expanded_a[expanded_index])
+ al.append(self.a[i])
+ eb.append(self._expanded_b[expanded_index])
+ bl.append(self.b[i])
+ eo.append(self._expanded_output[expanded_index])
+ ol.append(self.output[i])
expanded_index += 1
+ # combine above using Cat
+ m.d.comb += Cat(*ea).eq(Cat(*al))
+ m.d.comb += Cat(*eb).eq(Cat(*bl))
+ m.d.comb += Cat(*ol).eq(Cat(*eo))
# use only one addition to take advantage of look-ahead carry and
# special hardware on FPGAs
m.d.comb += self._expanded_output.eq(
FULL_ADDER_INPUT_COUNT = 3
-@final
class AddReduce(Elaboratable):
"""Add list of numbers together.
supported, except for by ``Signal.eq``.
"""
- def __init__(self,
- inputs: Iterable[Signal],
- output_width: int,
- register_levels: Iterable[int],
- partition_points: PartitionPointsIn):
+ def __init__(self, inputs, output_width, register_levels, partition_points):
"""Create an ``AddReduce``.
:param inputs: input ``Signal``s to be summed.
"not enough adder levels for specified register levels")
@staticmethod
- def get_max_level(input_count: int) -> int:
+ def get_max_level(input_count):
"""Get the maximum level.
All ``register_levels`` must be less than or equal to the maximum
input_count += 2 * len(groups)
retval += 1
- def next_register_levels(self) -> Iterable[int]:
+ def next_register_levels(self):
"""``Iterable`` of ``register_levels`` for next recursive level."""
for level in self.register_levels:
if level > 0:
yield level - 1
@staticmethod
- def full_adder_groups(input_count: int) -> range:
+ def full_adder_groups(input_count):
"""Get ``inputs`` indices for which a full adder should be built."""
return range(0,
input_count - FULL_ADDER_INPUT_COUNT + 1,
FULL_ADDER_INPUT_COUNT)
- def elaborate(self, platform: Any) -> Module:
+ def elaborate(self, platform):
"""Elaborate this module."""
m = Module()
m.d.comb += self.output.eq(adder.output)
return m
# go on to handle recursive case
- intermediate_terms: List[Signal]
intermediate_terms = []
- def add_intermediate_term(value: Value) -> None:
+ def add_intermediate_term(value):
intermediate_term = Signal(
len(self.output),
name=f"intermediate_terms[{len(intermediate_terms)}]")
intermediate_terms.append(intermediate_term)
m.d.comb += intermediate_term.eq(value)
- part_mask = self._reg_partition_points.as_mask(len(self.output))
+ # store mask in intermediary (simplifies graph)
+ part_mask = Signal(len(self.output), reset_less=True)
+ mask = self._reg_partition_points.as_mask(len(self.output))
+ m.d.comb += part_mask.eq(mask)
# create full adders for this recursive level.
# this shrinks N terms to 2 * (N // 3) plus the remainder
OP_MUL_UNSIGNED_HIGH = 3
+def get_term(value, shift=0, enabled=None):
+ if enabled is not None:
+ value = Mux(enabled, value, 0)
+ if shift > 0:
+ value = Cat(Repl(C(0, 1), shift), value)
+ else:
+ assert shift == 0
+ return value
+
+
+class Term(Elaboratable):
+ def __init__(self, width, twidth, shift=0, enabled=None):
+ self.width = width
+ self.shift = shift
+ self.enabled = enabled
+ self.ti = Signal(width, reset_less=True)
+ self.term = Signal(twidth, reset_less=True)
+
+ def elaborate(self, platform):
+
+ m = Module()
+ m.d.comb += self.term.eq(get_term(self.ti, self.shift, self.enabled))
+
+ return m
+
+
+class ProductTerm(Elaboratable):
+ def __init__(self, width, twidth, pbwid, a_index, b_index):
+ self.a_index = a_index
+ self.b_index = b_index
+ shift = 8 * (self.a_index + self.b_index)
+ self.pwidth = width
+ self.a = Signal(twidth, reset_less=True)
+ self.b = Signal(twidth, reset_less=True)
+ self.pb_en = Signal(pbwid, reset_less=True)
+
+ self.tl = tl = []
+ min_index = min(self.a_index, self.b_index)
+ max_index = max(self.a_index, self.b_index)
+ for i in range(min_index, max_index):
+ tl.append(self.pb_en[i])
+ name = "te_%d_%d" % (self.a_index, self.b_index)
+ if len(tl) > 0:
+ term_enabled = Signal(name=name, reset_less=True)
+ else:
+ term_enabled = None
+
+ Term.__init__(self, width*2, twidth, shift, term_enabled)
+ self.term.name = "term_%d_%d" % (a_index, b_index) # rename
+
+ def elaborate(self, platform):
+
+ m = Term.elaborate(self, platform)
+ if self.enabled is not None:
+ m.d.comb += self.enabled.eq(~(Cat(*self.tl).bool()))
+
+ bsa = Signal(self.width, reset_less=True)
+ bsb = Signal(self.width, reset_less=True)
+ a_index, b_index = self.a_index, self.b_index
+ pwidth = self.pwidth
+ m.d.comb += bsa.eq(self.a.bit_select(a_index * pwidth, pwidth))
+ m.d.comb += bsb.eq(self.b.bit_select(b_index * pwidth, pwidth))
+ m.d.comb += self.ti.eq(bsa * bsb)
+
+ return m
+
+
+class Part(Elaboratable):
+ def __init__(self, width, n_parts, n_levels, pbwid):
+
+ # inputs
+ self.a = Signal(64)
+ self.b = Signal(64)
+ self._a_signed = [Signal(name=f"_a_signed_{i}") for i in range(8)]
+ self._b_signed = [Signal(name=f"_b_signed_{i}") for i in range(8)]
+ self.pbs = Signal(pbwid, reset_less=True)
+
+ # outputs
+ self.parts = [Signal(name=f"part_{i}") for i in range(n_parts)]
+ self.delayed_parts = [
+ [Signal(name=f"delayed_part_8_{delay}_{i}")
+ for i in range(n_parts)]
+ for delay in range(n_levels)]
+
+ self.not_a_term = Signal(width)
+ self.neg_lsb_a_term = Signal(width)
+ self.not_b_term = Signal(width)
+ self.neg_lsb_b_term = Signal(width)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ pbs, parts, delayed_parts = self.pbs, self.parts, self.delayed_parts
+ byte_count = 8 // len(parts)
+ for i in range(len(parts)):
+ pbl = []
+ pbl.append(~pbs[i * byte_count - 1])
+ for j in range(i * byte_count, (i + 1) * byte_count - 1):
+ pbl.append(pbs[j])
+ pbl.append(~pbs[(i + 1) * byte_count - 1])
+ value = Signal(len(pbl), reset_less=True)
+ m.d.comb += value.eq(Cat(*pbl))
+ m.d.comb += parts[i].eq(~(value).bool())
+ m.d.comb += delayed_parts[0][i].eq(parts[i])
+ m.d.sync += [delayed_parts[j + 1][i].eq(delayed_parts[j][i])
+ for j in range(len(delayed_parts)-1)]
+
+ not_a_term, neg_lsb_a_term, not_b_term, neg_lsb_b_term = \
+ self.not_a_term, self.neg_lsb_a_term, \
+ self.not_b_term, self.neg_lsb_b_term
+
+ byte_width = 8 // len(parts)
+ bit_width = 8 * byte_width
+ nat, nbt, nla, nlb = [], [], [], []
+ for i in range(len(parts)):
+ be = parts[i] & self.a[(i + 1) * bit_width - 1] \
+ & self._a_signed[i * byte_width]
+ ae = parts[i] & self.b[(i + 1) * bit_width - 1] \
+ & self._b_signed[i * byte_width]
+ a_enabled = Signal(name="a_en_%d" % i, reset_less=True)
+ b_enabled = Signal(name="b_en_%d" % i, reset_less=True)
+ m.d.comb += a_enabled.eq(ae)
+ m.d.comb += b_enabled.eq(be)
+
+ # for 8-bit values: form a * 0xFF00 by using -a * 0x100, the
+ # negation operation is split into a bitwise not and a +1.
+ # likewise for 16, 32, and 64-bit values.
+ nat.append(Mux(a_enabled,
+ Cat(Repl(0, bit_width),
+ ~self.a.bit_select(bit_width * i, bit_width)),
+ 0))
+
+ nla.append(Cat(Repl(0, bit_width), a_enabled,
+ Repl(0, bit_width-1)))
+
+ nbt.append(Mux(b_enabled,
+ Cat(Repl(0, bit_width),
+ ~self.b.bit_select(bit_width * i, bit_width)),
+ 0))
+
+ nlb.append(Cat(Repl(0, bit_width), b_enabled,
+ Repl(0, bit_width-1)))
+
+ m.d.comb += [not_a_term.eq(Cat(*nat)),
+ not_b_term.eq(Cat(*nbt)),
+ neg_lsb_a_term.eq(Cat(*nla)),
+ neg_lsb_b_term.eq(Cat(*nlb)),
+ ]
+
+ return m
+
+
+class IntermediateOut(Elaboratable):
+ def __init__(self, width, out_wid, n_parts):
+ self.width = width
+ self.n_parts = n_parts
+ self.delayed_part_ops = [Signal(2, name="dpop%d" % i, reset_less=True)
+ for i in range(8)]
+ self.intermed = Signal(out_wid, reset_less=True)
+ self.output = Signal(out_wid//2, reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ ol = []
+ w = self.width
+ sel = w // 8
+ for i in range(self.n_parts):
+ op = Signal(w, reset_less=True, name="op32_%d" % i)
+ m.d.comb += op.eq(
+ Mux(self.delayed_part_ops[sel * i] == OP_MUL_LOW,
+ self.intermed.bit_select(i * w*2, w),
+ self.intermed.bit_select(i * w*2 + w, w)))
+ ol.append(op)
+ m.d.comb += self.output.eq(Cat(*ol))
+
+ return m
+
+
class Mul8_16_32_64(Elaboratable):
"""Signed/Unsigned 8/16/32/64-bit partitioned integer multiplier.
instruction.
"""
- def __init__(self, register_levels: Iterable[int] = ()):
+ def __init__(self, register_levels= ()):
self.part_pts = PartitionPoints()
for i in range(8, 64, 8):
self.part_pts[i] = Signal(name=f"part_pts_{i}")
self.output = Signal(64)
self.register_levels = list(register_levels)
self._intermediate_output = Signal(128)
- self._delayed_part_ops = [
- [Signal(2, name=f"_delayed_part_ops_{delay}_{i}")
- for i in range(8)]
- for delay in range(1 + len(self.register_levels))]
- self._part_8 = [Signal(name=f"_part_8_{i}") for i in range(8)]
- self._part_16 = [Signal(name=f"_part_16_{i}") for i in range(4)]
- self._part_32 = [Signal(name=f"_part_32_{i}") for i in range(2)]
- self._part_64 = [Signal(name=f"_part_64")]
- self._delayed_part_8 = [
- [Signal(name=f"_delayed_part_8_{delay}_{i}")
- for i in range(8)]
- for delay in range(1 + len(self.register_levels))]
- self._delayed_part_16 = [
- [Signal(name=f"_delayed_part_16_{delay}_{i}")
- for i in range(4)]
- for delay in range(1 + len(self.register_levels))]
- self._delayed_part_32 = [
- [Signal(name=f"_delayed_part_32_{delay}_{i}")
- for i in range(2)]
- for delay in range(1 + len(self.register_levels))]
- self._delayed_part_64 = [
- [Signal(name=f"_delayed_part_64_{delay}")]
- for delay in range(1 + len(self.register_levels))]
self._output_64 = Signal(64)
self._output_32 = Signal(64)
self._output_16 = Signal(64)
self._output_8 = Signal(64)
self._a_signed = [Signal(name=f"_a_signed_{i}") for i in range(8)]
self._b_signed = [Signal(name=f"_b_signed_{i}") for i in range(8)]
- self._not_a_term_8 = Signal(128)
- self._neg_lsb_a_term_8 = Signal(128)
- self._not_b_term_8 = Signal(128)
- self._neg_lsb_b_term_8 = Signal(128)
- self._not_a_term_16 = Signal(128)
- self._neg_lsb_a_term_16 = Signal(128)
- self._not_b_term_16 = Signal(128)
- self._neg_lsb_b_term_16 = Signal(128)
- self._not_a_term_32 = Signal(128)
- self._neg_lsb_a_term_32 = Signal(128)
- self._not_b_term_32 = Signal(128)
- self._neg_lsb_b_term_32 = Signal(128)
- self._not_a_term_64 = Signal(128)
- self._neg_lsb_a_term_64 = Signal(128)
- self._not_b_term_64 = Signal(128)
- self._neg_lsb_b_term_64 = Signal(128)
-
- def _part_byte(self, index: int) -> Value:
+
+ def _part_byte(self, index):
if index == -1 or index == 7:
return C(True, 1)
assert index >= 0 and index < 8
return self.part_pts[index * 8 + 8]
- def elaborate(self, platform: Any) -> Module:
+ def elaborate(self, platform):
m = Module()
+ # collect part-bytes
+ pbs = Signal(8, reset_less=True)
+ tl = []
+ for i in range(8):
+ pb = Signal(name="pb%d" % i, reset_less=True)
+ m.d.comb += pb.eq(self._part_byte(i))
+ tl.append(pb)
+ m.d.comb += pbs.eq(Cat(*tl))
+
+ delayed_part_ops = [
+ [Signal(2, name=f"_delayed_part_ops_{delay}_{i}")
+ for i in range(8)]
+ for delay in range(1 + len(self.register_levels))]
for i in range(len(self.part_ops)):
- m.d.comb += self._delayed_part_ops[0][i].eq(self.part_ops[i])
- m.d.sync += [self._delayed_part_ops[j + 1][i]
- .eq(self._delayed_part_ops[j][i])
+ m.d.comb += delayed_part_ops[0][i].eq(self.part_ops[i])
+ m.d.sync += [delayed_part_ops[j + 1][i].eq(delayed_part_ops[j][i])
for j in range(len(self.register_levels))]
- for parts, delayed_parts in [(self._part_64, self._delayed_part_64),
- (self._part_32, self._delayed_part_32),
- (self._part_16, self._delayed_part_16),
- (self._part_8, self._delayed_part_8)]:
- byte_count = 8 // len(parts)
- for i in range(len(parts)):
- value = self._part_byte(i * byte_count - 1)
- for j in range(i * byte_count, (i + 1) * byte_count - 1):
- value &= ~self._part_byte(j)
- value &= self._part_byte((i + 1) * byte_count - 1)
- m.d.comb += parts[i].eq(value)
- m.d.comb += delayed_parts[0][i].eq(parts[i])
- m.d.sync += [delayed_parts[j + 1][i].eq(delayed_parts[j][i])
- for j in range(len(self.register_levels))]
-
- products = [[
- Signal(16, name=f"products_{i}_{j}")
- for j in range(8)]
- for i in range(8)]
-
- for a_index in range(8):
- for b_index in range(8):
- a = self.a.part(a_index * 8, 8)
- b = self.b.part(b_index * 8, 8)
- m.d.comb += products[a_index][b_index].eq(a * b)
+ n_levels = len(self.register_levels)+1
+ m.submodules.part_8 = part_8 = Part(128, 8, n_levels, 8)
+ m.submodules.part_16 = part_16 = Part(128, 4, n_levels, 8)
+ m.submodules.part_32 = part_32 = Part(128, 2, n_levels, 8)
+ m.submodules.part_64 = part_64 = Part(128, 1, n_levels, 8)
+ nat_l, nbt_l, nla_l, nlb_l = [], [], [], []
+ for mod in [part_8, part_16, part_32, part_64]:
+ m.d.comb += mod.a.eq(self.a)
+ m.d.comb += mod.b.eq(self.b)
+ for i in range(len(self._a_signed)):
+ m.d.comb += mod._a_signed[i].eq(self._a_signed[i])
+ for i in range(len(self._b_signed)):
+ m.d.comb += mod._b_signed[i].eq(self._b_signed[i])
+ m.d.comb += mod.pbs.eq(pbs)
+ nat_l.append(mod.not_a_term)
+ nbt_l.append(mod.not_b_term)
+ nla_l.append(mod.neg_lsb_a_term)
+ nlb_l.append(mod.neg_lsb_b_term)
terms = []
- def add_term(value: Value,
- shift: int = 0,
- enabled: Optional[Value] = None) -> None:
- term = Signal(128)
- terms.append(term)
- if enabled is not None:
- value = Mux(enabled, value, 0)
- if shift > 0:
- value = Cat(Repl(C(0, 1), shift), value)
- else:
- assert shift == 0
- m.d.comb += term.eq(value)
-
for a_index in range(8):
for b_index in range(8):
- term_enabled: Value = C(True, 1)
- min_index = min(a_index, b_index)
- max_index = max(a_index, b_index)
- for i in range(min_index, max_index):
- term_enabled &= ~self._part_byte(i)
- add_term(products[a_index][b_index],
- 8 * (a_index + b_index),
- term_enabled)
+ t = ProductTerm(8, 128, 8, a_index, b_index)
+ setattr(m.submodules, "term_%d_%d" % (a_index, b_index), t)
+
+ m.d.comb += t.a.eq(self.a)
+ m.d.comb += t.b.eq(self.b)
+ m.d.comb += t.pb_en.eq(pbs)
+
+ terms.append(t.term)
for i in range(8):
a_signed = self.part_ops[i] != OP_MUL_UNSIGNED_HIGH
b_signed = (self.part_ops[i] == OP_MUL_LOW) \
- | (self.part_ops[i] == OP_MUL_SIGNED_HIGH)
+ | (self.part_ops[i] == OP_MUL_SIGNED_HIGH)
m.d.comb += self._a_signed[i].eq(a_signed)
m.d.comb += self._b_signed[i].eq(b_signed)
# it's fine to bitwise-or these together since they are never enabled
# at the same time
- add_term(self._not_a_term_8 | self._not_a_term_16
- | self._not_a_term_32 | self._not_a_term_64)
- add_term(self._neg_lsb_a_term_8 | self._neg_lsb_a_term_16
- | self._neg_lsb_a_term_32 | self._neg_lsb_a_term_64)
- add_term(self._not_b_term_8 | self._not_b_term_16
- | self._not_b_term_32 | self._not_b_term_64)
- add_term(self._neg_lsb_b_term_8 | self._neg_lsb_b_term_16
- | self._neg_lsb_b_term_32 | self._neg_lsb_b_term_64)
-
- for not_a_term, \
- neg_lsb_a_term, \
- not_b_term, \
- neg_lsb_b_term, \
- parts in [
- (self._not_a_term_8,
- self._neg_lsb_a_term_8,
- self._not_b_term_8,
- self._neg_lsb_b_term_8,
- self._part_8),
- (self._not_a_term_16,
- self._neg_lsb_a_term_16,
- self._not_b_term_16,
- self._neg_lsb_b_term_16,
- self._part_16),
- (self._not_a_term_32,
- self._neg_lsb_a_term_32,
- self._not_b_term_32,
- self._neg_lsb_b_term_32,
- self._part_32),
- (self._not_a_term_64,
- self._neg_lsb_a_term_64,
- self._not_b_term_64,
- self._neg_lsb_b_term_64,
- self._part_64),
- ]:
- byte_width = 8 // len(parts)
- bit_width = 8 * byte_width
- for i in range(len(parts)):
- b_enabled = parts[i] & self.a[(i + 1) * bit_width - 1] \
- & self._a_signed[i * byte_width]
- a_enabled = parts[i] & self.b[(i + 1) * bit_width - 1] \
- & self._b_signed[i * byte_width]
-
- # for 8-bit values: form a * 0xFF00 by using -a * 0x100, the
- # negation operation is split into a bitwise not and a +1.
- # likewise for 16, 32, and 64-bit values.
- m.d.comb += [
- not_a_term.part(bit_width * 2 * i, bit_width * 2)
- .eq(Mux(a_enabled,
- Cat(Repl(0, bit_width),
- ~self.a.part(bit_width * i, bit_width)),
- 0)),
-
- neg_lsb_a_term.part(bit_width * 2 * i, bit_width * 2)
- .eq(Cat(Repl(0, bit_width), a_enabled)),
-
- not_b_term.part(bit_width * 2 * i, bit_width * 2)
- .eq(Mux(b_enabled,
- Cat(Repl(0, bit_width),
- ~self.b.part(bit_width * i, bit_width)),
- 0)),
-
- neg_lsb_b_term.part(bit_width * 2 * i, bit_width * 2)
- .eq(Cat(Repl(0, bit_width), b_enabled))]
+ nat_l = reduce(or_, nat_l)
+ nbt_l = reduce(or_, nbt_l)
+ nla_l = reduce(or_, nla_l)
+ nlb_l = reduce(or_, nlb_l)
+ m.submodules.nat = nat = Term(128, 128)
+ m.submodules.nla = nla = Term(128, 128)
+ m.submodules.nbt = nbt = Term(128, 128)
+ m.submodules.nlb = nlb = Term(128, 128)
+ m.d.comb += nat.ti.eq(nat_l)
+ m.d.comb += nbt.ti.eq(nbt_l)
+ m.d.comb += nla.ti.eq(nla_l)
+ m.d.comb += nlb.ti.eq(nlb_l)
+ terms.append(nat.term)
+ terms.append(nla.term)
+ terms.append(nbt.term)
+ terms.append(nlb.term)
expanded_part_pts = PartitionPoints()
for i, v in self.part_pts.items():
- signal = Signal(name=f"expanded_part_pts_{i*2}")
+ signal = Signal(name=f"expanded_part_pts_{i*2}", reset_less=True)
expanded_part_pts[i * 2] = signal
m.d.comb += signal.eq(v)
expanded_part_pts)
m.submodules.add_reduce = add_reduce
m.d.comb += self._intermediate_output.eq(add_reduce.output)
- m.d.comb += self._output_64.eq(
- Mux(self._delayed_part_ops[-1][0] == OP_MUL_LOW,
- self._intermediate_output.part(0, 64),
- self._intermediate_output.part(64, 64)))
- for i in range(2):
- m.d.comb += self._output_32.part(i * 32, 32).eq(
- Mux(self._delayed_part_ops[-1][4 * i] == OP_MUL_LOW,
- self._intermediate_output.part(i * 64, 32),
- self._intermediate_output.part(i * 64 + 32, 32)))
- for i in range(4):
- m.d.comb += self._output_16.part(i * 16, 16).eq(
- Mux(self._delayed_part_ops[-1][2 * i] == OP_MUL_LOW,
- self._intermediate_output.part(i * 32, 16),
- self._intermediate_output.part(i * 32 + 16, 16)))
+ # create _output_64
+ m.submodules.io64 = io64 = IntermediateOut(64, 128, 1)
+ m.d.comb += io64.intermed.eq(self._intermediate_output)
+ for i in range(8):
+ m.d.comb += io64.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
+ m.d.comb += self._output_64.eq(io64.output)
+
+ # create _output_32
+ m.submodules.io32 = io32 = IntermediateOut(32, 128, 2)
+ m.d.comb += io32.intermed.eq(self._intermediate_output)
+ for i in range(8):
+ m.d.comb += io32.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
+ m.d.comb += self._output_32.eq(io32.output)
+
+ # create _output_16
+ m.submodules.io16 = io16 = IntermediateOut(16, 128, 4)
+ m.d.comb += io16.intermed.eq(self._intermediate_output)
+ for i in range(8):
+ m.d.comb += io16.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
+ m.d.comb += self._output_16.eq(io16.output)
+
+ # create _output_8
+ m.submodules.io8 = io8 = IntermediateOut(8, 128, 8)
+ m.d.comb += io8.intermed.eq(self._intermediate_output)
for i in range(8):
- m.d.comb += self._output_8.part(i * 8, 8).eq(
- Mux(self._delayed_part_ops[-1][i] == OP_MUL_LOW,
- self._intermediate_output.part(i * 16, 8),
- self._intermediate_output.part(i * 16 + 8, 8)))
+ m.d.comb += io8.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
+ m.d.comb += self._output_8.eq(io8.output)
+
+ # final output
+ ol = []
for i in range(8):
- m.d.comb += self.output.part(i * 8, 8).eq(
- Mux(self._delayed_part_8[-1][i]
- | self._delayed_part_16[-1][i // 2],
- Mux(self._delayed_part_8[-1][i],
- self._output_8.part(i * 8, 8),
- self._output_16.part(i * 8, 8)),
- Mux(self._delayed_part_32[-1][i // 4],
- self._output_32.part(i * 8, 8),
- self._output_64.part(i * 8, 8))))
+ op = Signal(8, reset_less=True, name="op%d" % i)
+ m.d.comb += op.eq(
+ Mux(part_8.delayed_parts[-1][i]
+ | part_16.delayed_parts[-1][i // 2],
+ Mux(part_8.delayed_parts[-1][i],
+ self._output_8.bit_select(i * 8, 8),
+ self._output_16.bit_select(i * 8, 8)),
+ Mux(part_32.delayed_parts[-1][i // 4],
+ self._output_32.bit_select(i * 8, 8),
+ self._output_64.bit_select(i * 8, 8))))
+ ol.append(op)
+ m.d.comb += self.output.eq(Cat(*ol))
return m
projects / ieee754fpu.git / blobdiff