self.a_index = a_index
self.b_index = b_index
shift = 8 * (self.a_index + self.b_index)
- self.width = width
- self.a = Signal(width, reset_less=True)
- self.b = Signal(width, reset_less=True)
+ self.pwidth = width
+ self.a = Signal(twidth//2, reset_less=True)
+ self.b = Signal(twidth//2, reset_less=True)
self.pb_en = Signal(pbwid, reset_less=True)
self.tl = tl = []
term_enabled = None
Term.__init__(self, width*2, twidth, shift, term_enabled)
+ self.term.name = "term_%d_%d" % (a_index, b_index) # rename
def elaborate(self, platform):
m = Term.elaborate(self, platform)
if self.enabled is not None:
m.d.comb += self.enabled.eq(~(Cat(*self.tl).bool()))
- m.d.comb += self.ti.eq(self.a * self.b)
+
+ bsa = Signal(self.width, reset_less=True)
+ bsb = Signal(self.width, reset_less=True)
+ a_index, b_index = self.a_index, self.b_index
+ pwidth = self.pwidth
+ m.d.comb += bsa.eq(self.a.bit_select(a_index * pwidth, pwidth))
+ m.d.comb += bsb.eq(self.b.bit_select(b_index * pwidth, pwidth))
+ m.d.comb += self.ti.eq(bsa * bsb)
return m
+
+class ProductTerms(Elaboratable):
+
+ def __init__(self, width, twidth, pbwid, a_index, blen):
+ self.a_index = a_index
+ self.blen = blen
+ self.pwidth = width
+ self.twidth = twidth
+ self.pbwid = pbwid
+ self.a = Signal(twidth//2, reset_less=True)
+ self.b = Signal(twidth//2, reset_less=True)
+ self.pb_en = Signal(pbwid, reset_less=True)
+ self.terms = [Signal(twidth, name="term%d"%i, reset_less=True) \
+ for i in range(blen)]
+
+ def elaborate(self, platform):
+
+ m = Module()
+
+ for b_index in range(self.blen):
+ t = ProductTerm(self.pwidth, self.twidth, self.pbwid,
+ self.a_index, b_index)
+ setattr(m.submodules, "term_%d" % b_index, t)
+
+ m.d.comb += t.a.eq(self.a)
+ m.d.comb += t.b.eq(self.b)
+ m.d.comb += t.pb_en.eq(self.pb_en)
+
+ m.d.comb += self.terms[b_index].eq(t.term)
+
+ return m
+
+
class Part(Elaboratable):
def __init__(self, width, n_parts, n_levels, pbwid):
return m
+class IntermediateOut(Elaboratable):
+ def __init__(self, width, out_wid, n_parts):
+ self.width = width
+ self.n_parts = n_parts
+ self.delayed_part_ops = [Signal(2, name="dpop%d" % i, reset_less=True)
+ for i in range(8)]
+ self.intermed = Signal(out_wid, reset_less=True)
+ self.output = Signal(out_wid//2, reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ ol = []
+ w = self.width
+ sel = w // 8
+ for i in range(self.n_parts):
+ op = Signal(w, reset_less=True, name="op32_%d" % i)
+ m.d.comb += op.eq(
+ Mux(self.delayed_part_ops[sel * i] == OP_MUL_LOW,
+ self.intermed.bit_select(i * w*2, w),
+ self.intermed.bit_select(i * w*2 + w, w)))
+ ol.append(op)
+ m.d.comb += self.output.eq(Cat(*ol))
+
+ return m
+
+class OrMod(Elaboratable):
+ def __init__(self, wid):
+ self.wid = wid
+ self.orin = [Signal(wid, name="orin%d" % i, reset_less=True)
+ for i in range(4)]
+ self.orout = Signal(wid, reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+ or1 = Signal(self.wid, reset_less=True)
+ or2 = Signal(self.wid, reset_less=True)
+ m.d.comb += or1.eq(self.orin[0] | self.orin[1])
+ m.d.comb += or2.eq(self.orin[2] | self.orin[3])
+ m.d.comb += self.orout.eq(or1 | or2)
+
+ return m
+
+
class Mul8_16_32_64(Elaboratable):
"""Signed/Unsigned 8/16/32/64-bit partitioned integer multiplier.
self.output = Signal(64)
self.register_levels = list(register_levels)
self._intermediate_output = Signal(128)
- self._delayed_part_ops = [
- [Signal(2, name=f"_delayed_part_ops_{delay}_{i}")
- for i in range(8)]
- for delay in range(1 + len(self.register_levels))]
self._output_64 = Signal(64)
self._output_32 = Signal(64)
self._output_16 = Signal(64)
tl.append(pb)
m.d.comb += pbs.eq(Cat(*tl))
+ delayed_part_ops = [
+ [Signal(2, name=f"_delayed_part_ops_{delay}_{i}")
+ for i in range(8)]
+ for delay in range(1 + len(self.register_levels))]
for i in range(len(self.part_ops)):
- m.d.comb += self._delayed_part_ops[0][i].eq(self.part_ops[i])
- m.d.sync += [self._delayed_part_ops[j + 1][i]
- .eq(self._delayed_part_ops[j][i])
+ m.d.comb += delayed_part_ops[0][i].eq(self.part_ops[i])
+ m.d.sync += [delayed_part_ops[j + 1][i].eq(delayed_part_ops[j][i])
for j in range(len(self.register_levels))]
n_levels = len(self.register_levels)+1
terms = []
for a_index in range(8):
- for b_index in range(8):
- t = ProductTerm(8, 128, 8, a_index, b_index)
- setattr(m.submodules, "term_%d_%d" % (a_index, b_index), t)
+ t = ProductTerms(8, 128, 8, a_index, 8)
+ setattr(m.submodules, "terms_%d" % a_index, t)
- m.d.comb += t.a.eq(self.a.bit_select(a_index * 8, 8))
- m.d.comb += t.b.eq(self.b.bit_select(b_index * 8, 8))
- m.d.comb += t.pb_en.eq(pbs)
+ m.d.comb += t.a.eq(self.a)
+ m.d.comb += t.b.eq(self.b)
+ m.d.comb += t.pb_en.eq(pbs)
- terms.append(t.term)
+ for term in t.terms:
+ terms.append(term)
for i in range(8):
a_signed = self.part_ops[i] != OP_MUL_UNSIGNED_HIGH
m.d.comb += self._a_signed[i].eq(a_signed)
m.d.comb += self._b_signed[i].eq(b_signed)
- # it's fine to bitwise-or these together since they are never enabled
+ # it's fine to bitwise-or data together since they are never enabled
# at the same time
- nat_l = reduce(or_, nat_l)
- nbt_l = reduce(or_, nbt_l)
- nla_l = reduce(or_, nla_l)
- nlb_l = reduce(or_, nlb_l)
- m.submodules.nat = nat = Term(128, 128)
- m.submodules.nla = nla = Term(128, 128)
- m.submodules.nbt = nbt = Term(128, 128)
- m.submodules.nlb = nlb = Term(128, 128)
- m.d.comb += nat.ti.eq(nat_l)
- m.d.comb += nbt.ti.eq(nbt_l)
- m.d.comb += nla.ti.eq(nla_l)
- m.d.comb += nlb.ti.eq(nlb_l)
- terms.append(nat.term)
- terms.append(nla.term)
- terms.append(nbt.term)
- terms.append(nlb.term)
+ m.submodules.nat_or = nat_or = OrMod(128)
+ m.submodules.nbt_or = nbt_or = OrMod(128)
+ m.submodules.nla_or = nla_or = OrMod(128)
+ m.submodules.nlb_or = nlb_or = OrMod(128)
+ for l, mod in [(nat_l, nat_or),
+ (nbt_l, nbt_or),
+ (nla_l, nla_or),
+ (nlb_l, nlb_or)]:
+ for i in range(len(l)):
+ m.d.comb += mod.orin[i].eq(l[i])
+ terms.append(mod.orout)
expanded_part_pts = PartitionPoints()
for i, v in self.part_pts.items():
expanded_part_pts)
m.submodules.add_reduce = add_reduce
m.d.comb += self._intermediate_output.eq(add_reduce.output)
- m.d.comb += self._output_64.eq(
- Mux(self._delayed_part_ops[-1][0] == OP_MUL_LOW,
- self._intermediate_output.bit_select(0, 64),
- self._intermediate_output.bit_select(64, 64)))
+ # create _output_64
+ m.submodules.io64 = io64 = IntermediateOut(64, 128, 1)
+ m.d.comb += io64.intermed.eq(self._intermediate_output)
+ for i in range(8):
+ m.d.comb += io64.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
+ m.d.comb += self._output_64.eq(io64.output)
# create _output_32
- ol = []
- for i in range(2):
- op = Signal(32, reset_less=True, name="op32_%d" % i)
- m.d.comb += op.eq(
- Mux(self._delayed_part_ops[-1][4 * i] == OP_MUL_LOW,
- self._intermediate_output.bit_select(i * 64, 32),
- self._intermediate_output.bit_select(i * 64 + 32, 32)))
- ol.append(op)
- m.d.comb += self._output_32.eq(Cat(*ol))
+ m.submodules.io32 = io32 = IntermediateOut(32, 128, 2)
+ m.d.comb += io32.intermed.eq(self._intermediate_output)
+ for i in range(8):
+ m.d.comb += io32.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
+ m.d.comb += self._output_32.eq(io32.output)
# create _output_16
- ol = []
- for i in range(4):
- op = Signal(16, reset_less=True, name="op16_%d" % i)
- m.d.comb += op.eq(
- Mux(self._delayed_part_ops[-1][2 * i] == OP_MUL_LOW,
- self._intermediate_output.bit_select(i * 32, 16),
- self._intermediate_output.bit_select(i * 32 + 16, 16)))
- ol.append(op)
- m.d.comb += self._output_16.eq(Cat(*ol))
+ m.submodules.io16 = io16 = IntermediateOut(16, 128, 4)
+ m.d.comb += io16.intermed.eq(self._intermediate_output)
+ for i in range(8):
+ m.d.comb += io16.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
+ m.d.comb += self._output_16.eq(io16.output)
# create _output_8
- ol = []
+ m.submodules.io8 = io8 = IntermediateOut(8, 128, 8)
+ m.d.comb += io8.intermed.eq(self._intermediate_output)
for i in range(8):
- op = Signal(8, reset_less=True, name="op8_%d" % i)
- m.d.comb += op.eq(
- Mux(self._delayed_part_ops[-1][i] == OP_MUL_LOW,
- self._intermediate_output.bit_select(i * 16, 8),
- self._intermediate_output.bit_select(i * 16 + 8, 8)))
- ol.append(op)
- m.d.comb += self._output_8.eq(Cat(*ol))
+ m.d.comb += io8.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
+ m.d.comb += self._output_8.eq(io8.output)
# final output
ol = []
projects / ieee754fpu.git / blobdiff