use FinalReduceData

[ieee754fpu.git] / src / ieee754 / part_mul_add / test / test_multiply.py

diff --git a/src/ieee754/part_mul_add/test/test_multiply.py b/src/ieee754/part_mul_add/test/test_multiply.py
index d96d45c138d97e8f88edc39bb4e49d202f7bb8dd..e893ecac649b3a80dba254d99af31cb509f5e855 100644 (file)
--- a/src/ieee754/part_mul_add/test/test_multiply.py
+++ b/src/ieee754/part_mul_add/test/test_multiply.py
@@ -153,7 +153,7 @@ class TestAddReduce(unittest.TestCase):
             for value in values:
                 v += value & mask
             y |= mask & v
-        output = (yield module.output)
+        output = (yield module.o.output)
         if gen_or_check == GenOrCheck.Check:
             self.assertEqual(y, output, f"0x{y:X} != 0x{output:X}")
         yield Tick()
@@ -250,7 +250,8 @@ class TestAddReduce(unittest.TestCase):
         module = AddReduce(inputs,
                            width,
                            register_levels,
-                           partition_points)
+                           partition_points,
+                           [])
         file_name = "add_reduce"
         if len(register_levels) != 0:
             file_name += f"-{'_'.join(map(repr, register_levels))}"
@@ -259,7 +260,7 @@ class TestAddReduce(unittest.TestCase):
                               [partition_4,
                                partition_8,
                                *inputs,
-                               module.output],
+                               module.o.output],
                               file_name) as sim:
             self.subtest_run_sim(input_count,
                                  sim,
@@ -525,14 +526,6 @@ class TestMul8_16_32_64(unittest.TestCase):
                  module.output]
         ports.extend(module.part_ops)
         ports.extend(module.part_pts.values())
-        for signals in module._delayed_part_ops:
-            ports.extend(signals)
-        ports += [module._output_64,
-                  module._output_32,
-                  module._output_16,
-                  module._output_8]
-        ports.extend(module._a_signed)
-        ports.extend(module._b_signed)
         with create_simulator(module, ports, file_name) as sim:
             def process(gen_or_check: GenOrCheck) -> AsyncProcessGenerator:
                 for a_signed in False, True: