add twin MSB alignment / denormalisation (from FPMUL)

[ieee754fpu.git] / src / ieee754 / pipeline.py

diff --git a/src/ieee754/pipeline.py b/src/ieee754/pipeline.py
index f2ec693379abb71dc8e83e03770440e4800564dd..f914e978b34e9f1e273ffd5559d287137946e8b2 100644 (file)
--- a/src/ieee754/pipeline.py
+++ b/src/ieee754/pipeline.py
@@ -5,13 +5,23 @@
 class PipelineSpec:
     """ Pipeline Specification base class.
 
-    :attribute width: FIXME: document
-    :attribute id_width: FIXME: document
-    :attribute opcode_width: FIXME: document
+    :attribute width: the IEEE754 FP bitwidth
+    :attribute id_wid: the Reservation Station muxid bitwidth
+    :attribute op_wid: an "operand bitwidth" passed down all stages
+    :attribute opkls: an optional class that is instantiated as the "operand"
+
+    See ieee754/fpcommon/getop FPPipeContext for how (where) PipelineSpec
+    is used.  FPPipeContext is passed down *every* stage of a pipeline
+    and contains the Reservation Station multiplexer ID as well as
+    an optional "operand".  This "operand" may be used to *change*
+    the behaviour of the pipeline.  In RISC-V terminology it would
+    typically be set to e.g. funct7 or parts thereof.
+
     """
 
-    def __init__(self, width, id_width, opcode_width):
+    def __init__(self, width, id_width, op_wid=0, opkls=None):
         """ Create a PipelineSpec. """
         self.width = width
-        self.id_width = id_width
-        self.opcode_width = opcode_width
+        self.id_wid = id_width
+        self.op_wid = op_wid
+        self.opkls = opkls