# set up clock request generator
pod_bits = 25
sync_bits = 26
+ need_bridge=False
if fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim', 'ulx3s',
- 'orangecrab']:
- if fpga in ['isim']:
+ 'orangecrab','orangecrab_isim', 'rcs_arctic_tern_bmc_card']:
+ if fpga in ['isim','orangecrab_isim']:
pod_bits = 5
sync_bits = 6
+ if fpga in ['orangecrab', 'orangecrab_sim',
+ 'rcs_arctic_tern_bmc_card']:
+ need_bridge=True
self.crg = ECP5CRG(clk_freq, dram_clk_freq=dram_clk_freq,
- pod_bits=pod_bits, sync_bits=sync_bits)
+ pod_bits=pod_bits, sync_bits=sync_bits,
+ need_bridge=need_bridge)
if fpga in ['arty_a7']:
self.crg = ArtyA7CRG(clk_freq)
if spi_0_pins is not None and fpga in ['sim',
'isim',
'rcs_arctic_tern_bmc_card',
+ 'orangecrab',
+ 'orangecrab_isim',
'versa_ecp5',
'versa_ecp5_85',
'arty_a7']:
if fpga in ['versa_ecp5',
'versa_ecp5_85',
'rcs_arctic_tern_bmc_card',
+ 'orangecrab',
+ 'orangecrab_isim',
'isim']:
spi0_is_lattice_ecp5_clk = True
# Ethernet MAC
if ethmac_0_pins is not None and fpga in ['versa_ecp5',
'versa_ecp5_85',
- 'isim']:
+ 'isim']: # not orangecrab
self.eth_irq = IRQLine()
# The OpenCores Ethernet MAC contains two independent Wishbone
# interfaces, a slave (configuration) interface and a master (DMA)
'orangecrab': OrangeCrabR0_2_85k_Platform,
'arty_a7': ArtyA7_100Platform,
'isim': IcarusVersaPlatform,
+ 'orangecrab_isim': IcarusVersaPlatform,
+ 'rcs_arctic_tern_bmc_card':None, #TODO
'sim': None,
}[fpga]
toolchain = {'arty_a7': "yosys_nextpnr",
'versa_ecp5': 'Trellis',
'versa_ecp5_85': 'Trellis',
- 'orangecrab': 'Trellis',
+ 'orangecrab_isim': 'Trellis',
'isim': 'Trellis',
'ulx3s': 'Trellis',
+ 'rcs_arctic_tern_bmc_card': 'Trellis',
'sim': None,
}.get(fpga, None)
dram_cls = {'arty_a7': None,
'versa_ecp5': MT41K64M16,
'versa_ecp5_85': MT41K64M16,
+ 'orangecrab': MT41K64M16,
+ 'orangecrab_isim': MT41K64M16,
#'versa_ecp5': MT41K256M16,
'ulx3s': None,
+ 'rcs_arctic_tern_bmc_card': None, #TODO
'sim': MT41K256M16,
'isim': MT41K64M16,
}.get(fpga, None)
clk_freq = 50e6
dram_clk_freq = 100e6
if fpga == 'arty_a7':
- clk_freq = 50e6
+ clk_freq = 27.0e6 # urrr "working" with the QSPI core (25 mhz does not)
if fpga == 'ulx3s':
clk_freq = 40.0e6
- if fpga == 'orangecrab':
+ if fpga == 'orangecrab' or fpga=='orangecrab_isim':
clk_freq = 50e6
# merge dram_clk_freq with clk_freq if the same
if platform is not None:
if fpga=="orangecrab":
# assumes an FT232 USB-UART soldered onto these two pins.
- orangecrab_uart = UARTResource(0, rx="N17", tx="M18")
+ orangecrab_uart = UARTResource(0, rx="M18", tx="N17")
platform.add_resources([orangecrab_uart])
uart_pins = platform.request("uart", 0)
# get DDR resource pins, disable if clock frequency is below 50 mhz for now
ddr_pins = None
if (enable_dram and platform is not None and
- fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim']): # not yet 'arty_a7',
+ fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim',
+ 'orangecrab','orangecrab_isim']): # not yet 'arty_a7',
ddr_pins = platform.request("ddr3", 0,
dir={"dq":"-", "dqs":"-"},
xdr={"rst": 4, "clk":4, "a":4,
platform.add_resources(spi_0_ios)
spi_0_pins = platform.request("spi_0", 0)
+ orangecrab_enable_spi = False
+ if orangecrab_enable_spi and platform is not None and \
+ fpga in ['orangecrab']:
+ # spi_flash_mosi <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
+ # spi_flash_miso <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
+ # spi_flash_wp_n <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
+ # spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z';
+ # cs_n="U17", clk="U16", miso="T18", mosi="U18", wp_n="R18", hold_n="N18"
+ # each pin needs a separate direction control
+ spi_0_ios = [
+ Resource("spi_0", 0,
+ Subsignal("dq0", Pins("U18", dir="io")), #mosi
+ Subsignal("dq1", Pins("T18", dir="io")), #miso
+ Subsignal("dq2", Pins("R18", dir="io")), #wp_n
+ Subsignal("dq3", Pins("N18", dir="io")), #hold_n
+ # We use USRMCLK instead for clk
+ # todo: read docs
+ Subsignal("cs_n", Pins("U17", dir="o")),
+ # Subsignal("clk", Pins("U16", dir="o")),
+ Attrs(PULLMODE="NONE", DRIVE="4", IO_TYPE="LVCMOS33"))
+ ]
+ platform.add_resources(spi_0_ios)
+ spi_0_pins = platform.request("spi_0", 0, dir={"cs_n":"o"},
+ xdr={"dq0":1, "dq1": 1,
+ "dq2":1, "dq3": 1,
+ "cs_n":0})
+
print ("spiflash pins", spi_0_pins)
# Get Ethernet RMII resource pins
if toolchain == 'Trellis':
# add -abc9 option to yosys synth_ecp5
- #os.environ['NMIGEN_synth_opts'] = '-abc9 -nowidelut'
- #os.environ['NMIGEN_synth_opts'] = '-abc9'
- os.environ['NMIGEN_synth_opts'] = '-nowidelut'
+ os.environ['NMIGEN_synth_opts'] = '-abc9' # speed
+ # os.environ['NMIGEN_synth_opts'] = '-nowidelut' # size
+
+ if toolchain == 'yosys_nextpnr':
+ # add --seed 2 to arty a7 compile-time options
+ freq = clk_freq/1e6
+ os.environ['NMIGEN_nextpnr_opts'] = '--seed 3 --freq %.1f' % freq
+ os.environ['NMIGEN_nextpnr_opts'] += ' --timing-allow-fail'
if platform is not None:
# build and upload it
- if fpga == 'isim':
+ if fpga == 'isim' or fpga == 'orangecrab_isim':
platform.build(soc, do_program=False,
do_build=True, build_dir="build_simsoc")
else:
projects / ls2.git / blobdiff