use internal latch qlq value instead of creating a separate sync register

[soc.git] / src / scoreboard / dependence_cell.py

diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py
index 649b44e283c1976a78f5c32afdbd65329294462f..242c5a435a81282959a4d0193fbcd1be42247f2e 100644 (file)
--- a/src/scoreboard/dependence_cell.py
+++ b/src/scoreboard/dependence_cell.py
@@ -42,21 +42,16 @@ class DepCell(Elaboratable):
         m = Module()
         m.submodules.l = l = SRLatch(sync=False) # async latch
 
-        # record current version of q in a sync'd register
-        cq = Signal() # resets to 0
-        m.d.sync += cq.eq(l.q)
-
         # reset on go HI, set on dest and issue
         m.d.comb += l.s.eq(self.issue_i & self.reg_i)
         m.d.comb += l.r.eq(self.go_i)
 
         # Function Unit "Forward Progress".
-        m.d.comb += self.fwd_o.eq((l.q) & self.hazard_i)# & ~self.issue_i)
+        m.d.comb += self.fwd_o.eq((l.q) & self.hazard_i) # & ~self.issue_i)
 
         # Register Select. Activated on go read/write and *current* latch set
-        m.d.comb += self.rsel_o.eq((cq | l.q) & self.go_i)
-
-        m.d.comb += self.q_o.eq(cq | l.q)
+        m.d.comb += self.q_o.eq(l.qlq)
+        m.d.comb += self.rsel_o.eq(self.q_o & self.go_i)
 
         return m
 
@@ -122,6 +117,12 @@ class DependenceCell(Elaboratable):
                        (src2_c, self.src2_i)]:
             m.d.comb += c.reg_i.eq(reg)
 
+        # wark-wark: yes, writing to the same reg you are reading is *NOT*
+        # a write-after-read hazard.
+        selfhazard = Signal(reset_less=False)
+        m.d.comb += selfhazard.eq((self.dest_i & self.src1_i) |
+                                  (self.dest_i & self.src2_i))
+
         # connect up hazard checks: read-after-write and write-after-read
         m.d.comb += dest_c.hazard_i.eq(self.rd_pend_i) # read-after-write
         m.d.comb += src1_c.hazard_i.eq(self.wr_pend_i) # write-after-read
@@ -137,6 +138,7 @@ class DependenceCell(Elaboratable):
         # to be accumulated to indicate if register is in use (globally)
         # after ORing, is fed back in to rd_pend_i / wr_pend_i
         m.d.comb += self.rd_rsel_o.eq(src1_c.q_o | src2_c.q_o)
+        #with m.If(~selfhazard):
         m.d.comb += self.wr_rsel_o.eq(dest_c.q_o)
 
         return m