move dependency cells to row class

[soc.git] / src / scoreboard / dependence_cell.py

diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py
index 18e8d75556ab0338e3021c81c52d587d01787063..a4cb8a2d27d9d7ee0ec1a8d28bde1f8ac4103031 100644 (file)
--- a/src/scoreboard/dependence_cell.py
+++ b/src/scoreboard/dependence_cell.py
@@ -1,6 +1,6 @@
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
-from nmigen import Module, Signal, Elaboratable
+from nmigen import Module, Signal, Elaboratable, Array
 from nmutil.latch import SRLatch
 
 
@@ -14,8 +14,8 @@ class DependenceCell(Elaboratable):
         self.src2_i = Signal(reset_less=True)     # oper2 in (top)
         self.issue_i = Signal(reset_less=True)    # Issue in (top)
 
-        self.go_write_i = Signal(reset_less=True) # Go Write in (left)
-        self.go_read_i = Signal(reset_less=True)  # Go Read in (left)
+        self.go_wr_i = Signal(reset_less=True) # Go Write in (left)
+        self.go_rd_i = Signal(reset_less=True)  # Go Read in (left)
 
         # for Register File Select Lines (vertical)
         self.dest_rsel_o = Signal(reset_less=True)  # dest reg sel (bottom)
@@ -29,31 +29,31 @@ class DependenceCell(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.dest_l = dest_l = SRLatch()
-        m.submodules.src1_l = src1_l = SRLatch()
-        m.submodules.src2_l = src2_l = SRLatch()
+        m.submodules.dest_l = dest_l = SRLatch() # clock-sync'd
+        m.submodules.src1_l = src1_l = SRLatch() # clock-sync'd
+        m.submodules.src2_l = src2_l = SRLatch() # clock-sync'd
 
-        # destination latch: reset on go_write HI, set on dest and issue
+        # destination latch: reset on go_wr HI, set on dest and issue
         m.d.comb += dest_l.s.eq(self.issue_i & self.dest_i)
-        m.d.comb += dest_l.r.eq(self.go_write_i)
+        m.d.comb += dest_l.r.eq(self.go_wr_i)
 
-        # src1 latch: reset on go_read HI, set on src1_i and issue
+        # src1 latch: reset on go_rd HI, set on src1_i and issue
         m.d.comb += src1_l.s.eq(self.issue_i & self.src1_i)
-        m.d.comb += src1_l.r.eq(self.go_read_i)
+        m.d.comb += src1_l.r.eq(self.go_rd_i)
 
-        # src2 latch: reset on go_read HI, set on op2_i and issue
+        # src2 latch: reset on go_rd HI, set on op2_i and issue
         m.d.comb += src2_l.s.eq(self.issue_i & self.src2_i)
-        m.d.comb += src2_l.r.eq(self.go_read_i)
+        m.d.comb += src2_l.r.eq(self.go_rd_i)
 
         # FU "Forward Progress" (read out horizontally)
-        m.d.comb += self.dest_fwd_o.eq(dest_l.qn & self.dest_i)
-        m.d.comb += self.src1_fwd_o.eq(src1_l.qn & self.src1_i)
-        m.d.comb += self.src2_fwd_o.eq(src2_l.qn & self.src2_i)
+        m.d.comb += self.dest_fwd_o.eq(dest_l.q & self.go_wr_i)
+        m.d.comb += self.src1_fwd_o.eq(src1_l.q & self.go_rd_i)
+        m.d.comb += self.src2_fwd_o.eq(src2_l.q & self.go_rd_i)
 
         # Register File Select (read out vertically)
-        m.d.comb += self.dest_rsel_o.eq(dest_l.qn & self.go_write_i)
-        m.d.comb += self.src1_rsel_o.eq(src1_l.qn & self.go_read_i)
-        m.d.comb += self.src2_rsel_o.eq(src2_l.qn & self.go_read_i)
+        m.d.comb += self.dest_rsel_o.eq(dest_l.q & self.dest_i)
+        m.d.comb += self.src1_rsel_o.eq(src1_l.q & self.src1_i)
+        m.d.comb += self.src2_rsel_o.eq(src2_l.q & self.src2_i)
 
         return m
 
@@ -62,8 +62,8 @@ class DependenceCell(Elaboratable):
         yield self.src1_i
         yield self.src2_i
         yield self.issue_i
-        yield self.go_write_i
-        yield self.go_read_i
+        yield self.go_wr_i
+        yield self.go_rd_i
         yield self.dest_rsel_o
         yield self.src1_rsel_o
         yield self.src2_rsel_o
@@ -75,6 +75,18 @@ class DependenceCell(Elaboratable):
         return list(self)
 
 
+class DependencyRow(Elaboratable):
+    def __init__(self, n_reg_col):
+        self.n_reg_col = n_reg_col
+        self.rcell = Array(DependenceCell() for f in range(self.n_reg_col))
+
+    def elaborate(self, platform):
+        m = Module()
+        for rn in range(self.n_reg_col):
+            setattr(m.submodules, "dm_r%d" % rn, self.rcell[rn])
+        return m
+
+
 def dcell_sim(dut):
     yield dut.dest_i.eq(1)
     yield dut.issue_i.eq(1)
@@ -88,13 +100,13 @@ def dcell_sim(dut):
     yield
     yield dut.issue_i.eq(0)
     yield
-    yield dut.go_read_i.eq(1)
+    yield dut.go_rd_i.eq(1)
     yield
-    yield dut.go_read_i.eq(0)
+    yield dut.go_rd_i.eq(0)
     yield
-    yield dut.go_write_i.eq(1)
+    yield dut.go_wr_i.eq(1)
     yield
-    yield dut.go_write_i.eq(0)
+    yield dut.go_wr_i.eq(0)
     yield
 
 def test_dcell():