ignore self-to-self read and write pending hazards

[soc.git] / src / scoreboard / dependence_cell.py

diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py
index 9a54e3a4b4f7f4a21c06f9038f92fa9fbe016687..b137f7aed8b37f056559f977a55c558cec37802b 100644 (file)
--- a/src/scoreboard/dependence_cell.py
+++ b/src/scoreboard/dependence_cell.py
@@ -51,7 +51,7 @@ class DepCell(Elaboratable):
         m.d.comb += l.r.eq(self.go_i)
 
         # Function Unit "Forward Progress".
-        m.d.comb += self.fwd_o.eq((cq | l.q) & self.hazard_i & ~self.issue_i)
+        m.d.comb += self.fwd_o.eq((l.q) & self.hazard_i & ~self.issue_i)
 
         # Register Select. Activated on go read/write and *current* latch set
         m.d.comb += self.rsel_o.eq((cq | l.q) & self.go_i)
@@ -122,6 +122,12 @@ class DependenceCell(Elaboratable):
                        (src2_c, self.src2_i)]:
             m.d.comb += c.reg_i.eq(reg)
 
+        # wark-wark: yes, writing to the same reg you are reading is *NOT*
+        # a write-after-read hazard.
+        selfhazard = Signal(reset_less=False)
+        m.d.comb += selfhazard.eq((self.dest_i & self.src1_i) |
+                                  (self.dest_i & self.src2_i))
+
         # connect up hazard checks: read-after-write and write-after-read
         m.d.comb += dest_c.hazard_i.eq(self.rd_pend_i) # read-after-write
         m.d.comb += src1_c.hazard_i.eq(self.wr_pend_i) # write-after-read
@@ -137,6 +143,7 @@ class DependenceCell(Elaboratable):
         # to be accumulated to indicate if register is in use (globally)
         # after ORing, is fed back in to rd_pend_i / wr_pend_i
         m.d.comb += self.rd_rsel_o.eq(src1_c.q_o | src2_c.q_o)
+        #with m.If(~selfhazard):
         m.d.comb += self.wr_rsel_o.eq(dest_c.q_o)
 
         return m