have to bring in a reset signal into the shadow units to get them to go to

[soc.git] / src / scoreboard / dependence_cell.py

diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py
index a45c5839785b05f0393080b7cf328b945abefa2a..e12f216302f2c1f64257d0e7b9508300be05bec3 100644 (file)
--- a/src/scoreboard/dependence_cell.py
+++ b/src/scoreboard/dependence_cell.py
@@ -31,6 +31,7 @@ class DepCell(Elaboratable):
         self.issue_i = Signal(reset_less=True)   # Issue in (top)
         self.hazard_i = Signal(reset_less=True)  # to check hazard
         self.go_i = Signal(reset_less=True)      # Go read/write in (left)
+        self.die_i = Signal(reset_less=True)     # Die in (left)
         self.q_o = Signal(reset_less=True)       # Latch out (register active)
 
         # for Register File Select Lines (vertical)
@@ -42,21 +43,16 @@ class DepCell(Elaboratable):
         m = Module()
         m.submodules.l = l = SRLatch(sync=False) # async latch
 
-        # record current version of q in a sync'd register
-        cq = Signal() # resets to 0
-        m.d.sync += cq.eq(l.q)
-
         # reset on go HI, set on dest and issue
         m.d.comb += l.s.eq(self.issue_i & self.reg_i)
-        m.d.comb += l.r.eq(self.go_i)
+        m.d.comb += l.r.eq(self.go_i | self.die_i)
 
         # Function Unit "Forward Progress".
-        m.d.comb += self.fwd_o.eq((l.q) & self.hazard_i)# & ~self.issue_i)
+        m.d.comb += self.fwd_o.eq((l.q) & self.hazard_i) # & ~self.issue_i)
 
         # Register Select. Activated on go read/write and *current* latch set
-        m.d.comb += self.rsel_o.eq((cq | l.q) & self.go_i)
-
-        m.d.comb += self.q_o.eq(cq | l.q)
+        m.d.comb += self.q_o.eq(l.qlq)
+        m.d.comb += self.rsel_o.eq(l.qlq & self.go_i)
 
         return m
 
@@ -65,6 +61,7 @@ class DepCell(Elaboratable):
         yield self.hazard_i
         yield self.issue_i
         yield self.go_i
+        yield self.die_i
         yield self.q_o
         yield self.rsel_o
         yield self.fwd_o
@@ -90,6 +87,7 @@ class DependenceCell(Elaboratable):
 
         self.go_wr_i = Signal(reset_less=True) # Go Write in (left)
         self.go_rd_i = Signal(reset_less=True)  # Go Read in (left)
+        self.go_die_i = Signal(reset_less=True) # Go Die in (left)
 
         # for Register File Select Lines (vertical)
         self.dest_rsel_o = Signal(reset_less=True)  # dest reg sel (bottom)
@@ -107,9 +105,10 @@ class DependenceCell(Elaboratable):
         m.submodules.src1_c = src1_c = DepCell()
         m.submodules.src2_c = src2_c = DepCell()
 
-        # connect issue
+        # connect issue and die
         for c in [dest_c, src1_c, src2_c]:
             m.d.comb += c.issue_i.eq(self.issue_i)
+            m.d.comb += c.die_i.eq(self.go_die_i)
 
         # connect go_rd / go_wr (dest->wr, src->rd)
         m.d.comb += dest_c.go_i.eq(self.go_wr_i)
@@ -129,8 +128,7 @@ class DependenceCell(Elaboratable):
                                   (self.dest_i & self.src2_i))
 
         # connect up hazard checks: read-after-write and write-after-read
-        with m.If(~selfhazard):
-            m.d.comb += dest_c.hazard_i.eq(self.rd_pend_i) # read-after-write
+        m.d.comb += dest_c.hazard_i.eq(self.rd_pend_i) # read-after-write
         m.d.comb += src1_c.hazard_i.eq(self.wr_pend_i) # write-after-read
         m.d.comb += src2_c.hazard_i.eq(self.wr_pend_i) # write-after-read
 
@@ -144,8 +142,8 @@ class DependenceCell(Elaboratable):
         # to be accumulated to indicate if register is in use (globally)
         # after ORing, is fed back in to rd_pend_i / wr_pend_i
         m.d.comb += self.rd_rsel_o.eq(src1_c.q_o | src2_c.q_o)
-        with m.If(~selfhazard):
-            m.d.comb += self.wr_rsel_o.eq(dest_c.q_o)
+        #with m.If(~selfhazard):
+        m.d.comb += self.wr_rsel_o.eq(dest_c.q_o)
 
         return m
 
@@ -158,6 +156,7 @@ class DependenceCell(Elaboratable):
         yield self.issue_i
         yield self.go_wr_i
         yield self.go_rd_i
+        yield self.go_die_i
         yield self.dest_rsel_o
         yield self.src1_rsel_o
         yield self.src2_rsel_o
@@ -189,6 +188,7 @@ class DependencyRow(Elaboratable):
         self.issue_i = Signal(reset_less=True)
         self.go_wr_i = Signal(reset_less=True)
         self.go_rd_i = Signal(reset_less=True)
+        self.go_die_i = Signal(reset_less=True)
 
         self.dest_rsel_o = Signal(n_reg_col, reset_less=True)
         self.src1_rsel_o = Signal(n_reg_col, reset_less=True)
@@ -235,13 +235,14 @@ class DependencyRow(Elaboratable):
                     ]
 
         # ---
-        # connect Dep issue_i/go_rd_i/go_wr_i to module issue_i/go_rd/go_wr
+        # connect Dep die/issue_i/go_rd_i/go_wr_i to module issue_i/go_rd/go_wr
         # ---
         for rn in range(self.n_reg_col):
             dc = rcell[rn]
             m.d.comb += [dc.go_rd_i.eq(self.go_rd_i),
                          dc.go_wr_i.eq(self.go_wr_i),
                          dc.issue_i.eq(self.issue_i),
+                         dc.go_die_i.eq(self.go_die_i),
                     ]
 
         # ---
@@ -288,6 +289,7 @@ class DependencyRow(Elaboratable):
         yield self.issue_i
         yield self.go_wr_i
         yield self.go_rd_i
+        yield self.go_die_i
         yield self.dest_rsel_o
         yield self.src1_rsel_o
         yield self.src2_rsel_o