extend ld/st mem test

[soc.git] / src / scoreboard / fu_dep_cell.py

diff --git a/src/scoreboard/fu_dep_cell.py b/src/scoreboard/fu_dep_cell.py
index 4ac2a6daa76034c20339cb74bb2708259456e3eb..9946dcb5632c4da8dfb820cb46ac1968f7aaf0d4 100644 (file)
--- a/src/scoreboard/fu_dep_cell.py
+++ b/src/scoreboard/fu_dep_cell.py
@@ -1,80 +1,48 @@
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
-from nmigen import Module, Signal, Elaboratable
+from nmigen import Module, Signal, Const, Elaboratable
 from nmutil.latch import SRLatch
 
 
-class DepCell(Elaboratable):
-    """ FU Dependency Cell
-    """
-    def __init__(self):
-        # inputs
-        self.pend_i = Signal(reset_less=True)    # pending bit in (left)
-        self.issue_i = Signal(reset_less=True)   # Issue in (top)
-        self.go_i = Signal(reset_less=True)      # Go read/write in (left)
-
-        # wait
-        self.wait_o = Signal(reset_less=True)  # wait out (right)
-
-    def elaborate(self, platform):
-        m = Module()
-        m.submodules.l = l = SRLatch(sync=False) # async latch
-
-        # reset on go HI, set on dest and issue
-        m.d.comb += l.s.eq(self.issue_i & self.pend_i)
-        m.d.comb += l.r.eq(self.go_i)
-
-        # wait out
-        m.d.comb += self.wait_o.eq(l.qlq & ~self.issue_i)
-
-        return m
-
-    def __iter__(self):
-        yield self.pend_i
-        yield self.issue_i
-        yield self.go_i
-        yield self.wait_o
-
-    def ports(self):
-        return list(self)
-
-
 class FUDependenceCell(Elaboratable):
     """ implements 11.4.7 mitch alsup dependence cell, p27
     """
-    def __init__(self):
+    def __init__(self, dummy, n_fu=1):
+        self.n_fu = n_fu
+        self.dummy = Const(~(1<<dummy), n_fu)
         # inputs
-        self.rd_pend_i = Signal(reset_less=True)     # read pending in (left)
-        self.wr_pend_i = Signal(reset_less=True)     # write pending in (left)
-        self.issue_i = Signal(reset_less=True)    # Issue in (top)
+        self.rd_pend_i = Signal(n_fu, reset_less=True) # read pend in (left)
+        self.wr_pend_i = Signal(n_fu, reset_less=True) # write pend in (left)
+        self.issue_i = Signal(n_fu, reset_less=True)    # Issue in (top)
 
-        self.go_wr_i = Signal(reset_less=True) # Go Write in (left)
-        self.go_rd_i = Signal(reset_less=True)  # Go Read in (left)
+        self.go_wr_i = Signal(n_fu, reset_less=True) # Go Write in (left)
+        self.go_rd_i = Signal(n_fu, reset_less=True)  # Go Read in (left)
+        self.go_die_i = Signal(n_fu, reset_less=True) # Go Die in (left)
 
         # outputs (latched rd/wr wait)
-        self.rd_wait_o = Signal(reset_less=True)   # read waiting out (right)
-        self.wr_wait_o = Signal(reset_less=True)   # write waiting out (right)
+        self.rd_wait_o = Signal(n_fu, reset_less=True) # read wait out (right)
+        self.wr_wait_o = Signal(n_fu, reset_less=True) # write wait out (right)
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.rd_c = rd_c = DepCell()
-        m.submodules.wr_c = wr_c = DepCell()
+        m.submodules.rd_c = rd_c = SRLatch(sync=False, llen=self.n_fu)
+        m.submodules.wr_c = wr_c = SRLatch(sync=False, llen=self.n_fu)
 
-        # connect issue
-        for c in [rd_c, wr_c]:
-            m.d.comb += c.issue_i.eq(self.issue_i)
+        # reset on go HI, set on dest and issue
+        m.d.comb += rd_c.s.eq(self.issue_i & self.rd_pend_i)
+        m.d.comb += wr_c.s.eq(self.issue_i & self.wr_pend_i)
 
         # connect go_rd / go_wr 
-        m.d.comb += wr_c.go_i.eq(self.go_wr_i)
-        m.d.comb += rd_c.go_i.eq(self.go_rd_i)
+        m.d.comb += wr_c.r.eq(self.go_wr_i | self.go_die_i)
+        m.d.comb += rd_c.r.eq(self.go_rd_i | self.go_die_i)
 
         # connect pend_i
-        m.d.comb += wr_c.pend_i.eq(self.wr_pend_i)
-        m.d.comb += rd_c.pend_i.eq(self.rd_pend_i)
+        m.d.comb += rd_c.s.eq(self.issue_i & self.rd_pend_i & self.dummy)
+        m.d.comb += wr_c.s.eq(self.issue_i & self.wr_pend_i & self.dummy)
 
         # connect output
-        m.d.comb += self.wr_wait_o.eq(wr_c.wait_o)
-        m.d.comb += self.rd_wait_o.eq(rd_c.wait_o)
+        m.d.comb += self.rd_wait_o.eq(rd_c.qlq & ~self.issue_i)
+        m.d.comb += self.wr_wait_o.eq(wr_c.qlq & ~self.issue_i)
 
         return m
 
@@ -84,6 +52,7 @@ class FUDependenceCell(Elaboratable):
         yield self.issue_i
         yield self.go_wr_i
         yield self.go_rd_i
+        yield self.go_die_i
         yield self.rd_wait_o
         yield self.wr_wait_o
                 
@@ -112,7 +81,7 @@ def dcell_sim(dut):
     yield
 
 def test_dcell():
-    dut = FUDependenceCell()
+    dut = FUDependenceCell(dummy=0, n_fu=4)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_fu_dcell.il", "w") as f:
         f.write(vl)