use loop around src nums in FU Reg Matrix

[soc.git] / src / scoreboard / fu_dep_cell.py

diff --git a/src/scoreboard/fu_dep_cell.py b/src/scoreboard/fu_dep_cell.py
index 93ef28d3cbd82f609f585225960ce2ed06702169..9946dcb5632c4da8dfb820cb46ac1968f7aaf0d4 100644 (file)
--- a/src/scoreboard/fu_dep_cell.py
+++ b/src/scoreboard/fu_dep_cell.py
@@ -1,41 +1,48 @@
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
-from nmigen import Module, Signal, Elaboratable
+from nmigen import Module, Signal, Const, Elaboratable
 from nmutil.latch import SRLatch
 
 
 class FUDependenceCell(Elaboratable):
     """ implements 11.4.7 mitch alsup dependence cell, p27
     """
-    def __init__(self):
+    def __init__(self, dummy, n_fu=1):
+        self.n_fu = n_fu
+        self.dummy = Const(~(1<<dummy), n_fu)
         # inputs
-        self.rd_pend_i = Signal(reset_less=True)     # read pending in (left)
-        self.wr_pend_i = Signal(reset_less=True)     # write pending in (left)
-        self.issue_i = Signal(reset_less=True)    # Issue in (top)
+        self.rd_pend_i = Signal(n_fu, reset_less=True) # read pend in (left)
+        self.wr_pend_i = Signal(n_fu, reset_less=True) # write pend in (left)
+        self.issue_i = Signal(n_fu, reset_less=True)    # Issue in (top)
 
-        self.go_write_i = Signal(reset_less=True) # Go Write in (left)
-        self.go_read_i = Signal(reset_less=True)  # Go Read in (left)
+        self.go_wr_i = Signal(n_fu, reset_less=True) # Go Write in (left)
+        self.go_rd_i = Signal(n_fu, reset_less=True)  # Go Read in (left)
+        self.go_die_i = Signal(n_fu, reset_less=True) # Go Die in (left)
 
-        # outputs (latched rd/wr pend)
-        self.rd_pend_o = Signal(reset_less=True)   # read pending out (right)
-        self.wr_pend_o = Signal(reset_less=True)   # write pending out (right)
+        # outputs (latched rd/wr wait)
+        self.rd_wait_o = Signal(n_fu, reset_less=True) # read wait out (right)
+        self.wr_wait_o = Signal(n_fu, reset_less=True) # write wait out (right)
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.rd_l = rd_l = SRLatch()
-        m.submodules.wr_l = wr_l = SRLatch()
+        m.submodules.rd_c = rd_c = SRLatch(sync=False, llen=self.n_fu)
+        m.submodules.wr_c = wr_c = SRLatch(sync=False, llen=self.n_fu)
 
-        # write latch: reset on go_write HI, set on write pending and issue
-        m.d.comb += wr_l.s.eq(self.issue_i & self.wr_pend_i)
-        m.d.comb += wr_l.r.eq(self.go_write_i)
+        # reset on go HI, set on dest and issue
+        m.d.comb += rd_c.s.eq(self.issue_i & self.rd_pend_i)
+        m.d.comb += wr_c.s.eq(self.issue_i & self.wr_pend_i)
 
-        # read latch: reset on go_read HI, set on read pending and issue
-        m.d.comb += rd_l.s.eq(self.issue_i & self.rd_pend_i)
-        m.d.comb += rd_l.r.eq(self.go_read_i)
+        # connect go_rd / go_wr 
+        m.d.comb += wr_c.r.eq(self.go_wr_i | self.go_die_i)
+        m.d.comb += rd_c.r.eq(self.go_rd_i | self.go_die_i)
 
-        # Read/Write Pending Latches (read out horizontally)
-        m.d.comb += self.wr_pend_o.eq(wr_l.qn)
-        m.d.comb += self.rd_pend_o.eq(rd_l.qn)
+        # connect pend_i
+        m.d.comb += rd_c.s.eq(self.issue_i & self.rd_pend_i & self.dummy)
+        m.d.comb += wr_c.s.eq(self.issue_i & self.wr_pend_i & self.dummy)
+
+        # connect output
+        m.d.comb += self.rd_wait_o.eq(rd_c.qlq & ~self.issue_i)
+        m.d.comb += self.wr_wait_o.eq(wr_c.qlq & ~self.issue_i)
 
         return m
 
@@ -43,10 +50,11 @@ class FUDependenceCell(Elaboratable):
         yield self.rd_pend_i
         yield self.wr_pend_i
         yield self.issue_i
-        yield self.go_write_i
-        yield self.go_read_i
-        yield self.rd_pend_o
-        yield self.wr_pend_o
+        yield self.go_wr_i
+        yield self.go_rd_i
+        yield self.go_die_i
+        yield self.rd_wait_o
+        yield self.wr_wait_o
                 
     def ports(self):
         return list(self)
@@ -63,17 +71,17 @@ def dcell_sim(dut):
     yield
     yield dut.issue_i.eq(0)
     yield
-    yield dut.go_read_i.eq(1)
+    yield dut.go_rd_i.eq(1)
     yield
-    yield dut.go_read_i.eq(0)
+    yield dut.go_rd_i.eq(0)
     yield
-    yield dut.go_write_i.eq(1)
+    yield dut.go_wr_i.eq(1)
     yield
-    yield dut.go_write_i.eq(0)
+    yield dut.go_wr_i.eq(0)
     yield
 
 def test_dcell():
-    dut = FUDependenceCell()
+    dut = FUDependenceCell(dummy=0, n_fu=4)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_fu_dcell.il", "w") as f:
         f.write(vl)