invert x/y in fu pending

[soc.git] / src / scoreboard / fu_fu_matrix.py

diff --git a/src/scoreboard/fu_fu_matrix.py b/src/scoreboard/fu_fu_matrix.py
index a73cde9c2671d83d8915dd4d344b865bcb1c9138..bb7f8b18bafea0088dae45732cc9c3037f8a7512 100644 (file)
--- a/src/scoreboard/fu_fu_matrix.py
+++ b/src/scoreboard/fu_fu_matrix.py
@@ -56,27 +56,32 @@ class FUFUDepMatrix(Elaboratable):
         writable = []
         for x in range(self.n_fu_col):
             fu = fur[x]
-            rd_pend_o = []
-            wr_pend_o = []
-            for y in range(self.n_fu_row):
-                dc = dm[x][y]
-                # accumulate cell outputs rd/wr-pending
-                rd_pend_o.append(dc.rd_pend_o)
-                wr_pend_o.append(dc.wr_pend_o)
-            # connect cell reg-select outputs to Reg Vector In
-            m.d.comb += [fu.rd_pend_i.eq(Cat(*rd_pend_o)),
-                         fu.wr_pend_i.eq(Cat(*wr_pend_o)),
-                        ]
             # accumulate Readable/Writable Vector outputs
             readable.append(fu.readable_o)
             writable.append(fu.writable_o)
 
         # ... and output them from this module (horizontal, width=REGs)
-        m.d.comb += self.readable_o.eq(Cat(*readable))
-        m.d.comb += self.writable_o.eq(Cat(*writable))
+        m.d.comb += self.readable_o.eq(Cat(*writable))
+        m.d.comb += self.writable_o.eq(Cat(*readable))
 
         # ---
-        # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
+        # connect FU Pending
+        # ---
+        for y in range(self.n_fu_row):
+            fu = fur[y]
+            rd_wait_o = []
+            wr_wait_o = []
+            for x in range(self.n_fu_col):
+                dc = dm[x][y]
+                # accumulate cell outputs rd/wr-pending
+                rd_wait_o.append(dc.rd_wait_o)
+                wr_wait_o.append(dc.wr_wait_o)
+            # connect cell reg-select outputs to Reg Vector In
+            m.d.comb += [fu.rd_pend_i.eq(Cat(*rd_wait_o)),
+                         fu.wr_pend_i.eq(Cat(*wr_wait_o)),
+                        ]
+        # ---
+        # connect Dependency Matrix issue to module issue
         # ---
         for y in range(self.n_fu_row):
             issue_i = []
@@ -90,9 +95,23 @@ class FUFUDepMatrix(Elaboratable):
         # ---
         # connect Matrix go_rd_i/go_wr_i to module readable/writable
         # ---
-        for x in range(self.n_fu_col):
+        for y in range(self.n_fu_row):
             go_rd_i = []
             go_wr_i = []
+            for x in range(self.n_fu_col):
+                dc = dm[x][y]
+                # accumulate cell go_rd/go_wr
+                go_rd_i.append(dc.go_rd_i)
+                go_wr_i.append(dc.go_wr_i)
+            # wire up inputs from module to row cell inputs (Cat is gooood)
+            m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i),
+                         Cat(*go_wr_i).eq(self.go_wr_i),
+                        ]
+
+        # ---
+        # connect Matrix pending
+        # ---
+        for x in range(self.n_fu_col):
             rd_pend_i = []
             wr_pend_i = []
             for y in range(self.n_fu_row):
@@ -100,12 +119,8 @@ class FUFUDepMatrix(Elaboratable):
                 # accumulate cell rd_pend/wr_pend/go_rd/go_wr
                 rd_pend_i.append(dc.rd_pend_i)
                 wr_pend_i.append(dc.wr_pend_i)
-                go_rd_i.append(dc.go_rd_i)
-                go_wr_i.append(dc.go_wr_i)
             # wire up inputs from module to row cell inputs (Cat is gooood)
-            m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i),
-                         Cat(*go_wr_i).eq(self.go_wr_i),
-                         Cat(*rd_pend_i).eq(self.rd_pend_i),
+            m.d.comb += [Cat(*rd_pend_i).eq(self.rd_pend_i),
                          Cat(*wr_pend_i).eq(self.wr_pend_i),
                         ]