clean up names, also note that readable is true if no writes are pending

[soc.git] / src / scoreboard / fu_fu_matrix.py

diff --git a/src/scoreboard/fu_fu_matrix.py b/src/scoreboard/fu_fu_matrix.py
index 965503a93dec3a61faff2f72726e7c56ef8154bc..d8eaa8588c42eb8712d463109da2e9ce12c418c8 100644 (file)
--- a/src/scoreboard/fu_fu_matrix.py
+++ b/src/scoreboard/fu_fu_matrix.py
@@ -1,6 +1,6 @@
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
-from nmigen import Module, Signal, Elaboratable, Array, Cat
+from nmigen import Module, Signal, Elaboratable, Array, Cat, Const
 
 #from nmutil.latch import SRLatch
 from .fu_dep_cell import FUDependenceCell
@@ -67,11 +67,11 @@ class FUFUDepMatrix(Elaboratable):
         # ---
         # connect FU Pending
         # ---
-        for x in range(self.n_fu_col):
-            fu = fur[x]
+        for y in range(self.n_fu_row):
+            fu = fur[y]
             rd_wait_o = []
             wr_wait_o = []
-            for y in range(self.n_fu_row):
+            for x in range(self.n_fu_col):
                 dc = dm[x][y]
                 # accumulate cell outputs rd/wr-pending
                 rd_wait_o.append(dc.rd_wait_o)
@@ -83,9 +83,9 @@ class FUFUDepMatrix(Elaboratable):
         # ---
         # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
         # ---
-        for y in range(self.n_fu_row):
+        for x in range(self.n_fu_col):
             issue_i = []
-            for x in range(self.n_fu_col):
+            for y in range(self.n_fu_row):
                 dc = dm[x][y]
                 # accumulate cell inputs issue
                 issue_i.append(dc.issue_i)
@@ -95,22 +95,38 @@ class FUFUDepMatrix(Elaboratable):
         # ---
         # connect Matrix go_rd_i/go_wr_i to module readable/writable
         # ---
-        for x in range(self.n_fu_col):
+        for y in range(self.n_fu_row):
             go_rd_i = []
             go_wr_i = []
+            for x in range(self.n_fu_col):
+                dc = dm[x][y]
+                # accumulate cell go_rd/go_wr
+                go_rd_i.append(dc.go_rd_i)
+                go_wr_i.append(dc.go_wr_i)
+            # wire up inputs from module to row cell inputs (Cat is gooood)
+            m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i),
+                         Cat(*go_wr_i).eq(self.go_wr_i),
+                        ]
+
+        # ---
+        # connect Matrix pending
+        # ---
+        for y in range(self.n_fu_row):
             rd_pend_i = []
             wr_pend_i = []
-            for y in range(self.n_fu_row):
+            for x in range(self.n_fu_col):
+                if x == y: # ignore hazards on the diagonal: self-against-self
+                    dummyrd = Signal(reset_less=True)
+                    dummywr = Signal(reset_less=True)
+                    rd_pend_i.append(dummyrd)
+                    wr_pend_i.append(dummywr)
+                    continue
                 dc = dm[x][y]
                 # accumulate cell rd_pend/wr_pend/go_rd/go_wr
                 rd_pend_i.append(dc.rd_pend_i)
                 wr_pend_i.append(dc.wr_pend_i)
-                go_rd_i.append(dc.go_rd_i)
-                go_wr_i.append(dc.go_wr_i)
             # wire up inputs from module to row cell inputs (Cat is gooood)
-            m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i),
-                         Cat(*go_wr_i).eq(self.go_wr_i),
-                         Cat(*rd_pend_i).eq(self.rd_pend_i),
+            m.d.comb += [Cat(*rd_pend_i).eq(self.rd_pend_i),
                          Cat(*wr_pend_i).eq(self.wr_pend_i),
                         ]