from nmigen.compat.sim import run_simulation
from nmigen.cli import verilog, rtlil
-from nmigen import Module, Signal, Elaboratable, Array, Cat
+from nmigen import Module, Signal, Elaboratable, Array, Cat, Const
#from nmutil.latch import SRLatch
from .fu_dep_cell import FUDependenceCell
writable.append(fu.writable_o)
# ... and output them from this module (horizontal, width=REGs)
- m.d.comb += self.readable_o.eq(Cat(*writable))
- m.d.comb += self.writable_o.eq(Cat(*readable))
+ m.d.comb += self.readable_o.eq(Cat(*readable))
+ m.d.comb += self.writable_o.eq(Cat(*writable))
# ---
# connect FU Pending
# ---
for y in range(self.n_fu_row):
- fu = fur[x]
+ fu = fur[y]
rd_wait_o = []
wr_wait_o = []
for x in range(self.n_fu_col):
fu.wr_pend_i.eq(Cat(*wr_wait_o)),
]
# ---
- # connect Dependency Matrix issue to module issue
+ # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
# ---
- for y in range(self.n_fu_row):
+ for x in range(self.n_fu_col):
issue_i = []
- for x in range(self.n_fu_col):
+ for y in range(self.n_fu_row):
dc = dm[x][y]
# accumulate cell inputs issue
issue_i.append(dc.issue_i)
# ---
# connect Matrix pending
# ---
- for x in range(self.n_fu_col):
+ for y in range(self.n_fu_row):
rd_pend_i = []
wr_pend_i = []
- for y in range(self.n_fu_row):
+ for x in range(self.n_fu_col):
+ if x == y: # ignore hazards on the diagonal: self-against-self
+ dummyrd = Signal(reset_less=True)
+ dummywr = Signal(reset_less=True)
+ rd_pend_i.append(dummyrd)
+ wr_pend_i.append(dummywr)
+ continue
dc = dm[x][y]
# accumulate cell rd_pend/wr_pend/go_rd/go_wr
rd_pend_i.append(dc.rd_pend_i)