convert SPRs and others to Data.data/ok

[soc.git] / src / scoreboard / global_pending.py

diff --git a/src/scoreboard/global_pending.py b/src/scoreboard/global_pending.py
index f8ab4015b54226d7f8e558aad726f99664fae0d4..540f44306132e2fc0b7c62a730fb929d7a61ec24 100644 (file)
--- a/src/scoreboard/global_pending.py
+++ b/src/scoreboard/global_pending.py
@@ -1,8 +1,6 @@
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 from nmigen import Module, Signal, Cat, Elaboratable
-from nmutil.latch import SRLatch
-from nmigen.lib.coding import Decoder
 
 
 class GlobalPending(Elaboratable):
@@ -26,25 +24,29 @@ class GlobalPending(Elaboratable):
           on a particular register (extremely unusual), they must set a Const
           zero bit in the vector.
     """
-    def __init__(self, dep, fu_vecs):
+    def __init__(self, dep, fu_vecs, sync=False):
         self.reg_dep = dep
         # inputs
         self.fu_vecs = fu_vecs
+        self.sync = sync
         for v in fu_vecs:
             assert len(v) == dep, "FU Vector must be same width as regfile"
 
-        self.g_pend_o = Signal(wid, reset_less=True)  # global pending vector
+        self.g_pend_o = Signal(dep, reset_less=True)  # global pending vector
 
     def elaborate(self, platform):
         m = Module()
 
         pend_l = []
-        for i in range(self.reg_width): # per-register
+        for i in range(self.reg_dep): # per-register
             vec_bit_l = []
             for v in self.fu_vecs:
                 vec_bit_l.append(v[i])             # fu bit for same register
             pend_l.append(Cat(*vec_bit_l).bool())  # OR all bits for same reg
-        m.d.comb += self.g_pend_o.eq(Cat(*pend_l)) # merge all OR'd bits
+        if self.sync:
+            m.d.sync += self.g_pend_o.eq(Cat(*pend_l)) # merge all OR'd bits
+        else:
+            m.d.comb += self.g_pend_o.eq(Cat(*pend_l)) # merge all OR'd bits
 
         return m