extend ld/st mem test

[soc.git] / src / scoreboard / global_pending.py

diff --git a/src/scoreboard/global_pending.py b/src/scoreboard/global_pending.py
index 50e43378e76e112f22d548878b21ed218215615c..540f44306132e2fc0b7c62a730fb929d7a61ec24 100644 (file)
--- a/src/scoreboard/global_pending.py
+++ b/src/scoreboard/global_pending.py
@@ -1,8 +1,6 @@
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 from nmigen import Module, Signal, Cat, Elaboratable
-from nmutil.latch import SRLatch
-from nmigen.lib.coding import Decoder
 
 
 class GlobalPending(Elaboratable):
@@ -11,7 +9,7 @@ class GlobalPending(Elaboratable):
         Pending.  Can be used for INT or FP Global Pending.
 
         Inputs:
-        * :wid:       register file width
+        * :dep:       register file depth
         * :fu_vecs:   a python list of function unit "pending" vectors, each
                       vector being a Signal of width equal to the reg file.
 
@@ -26,25 +24,29 @@ class GlobalPending(Elaboratable):
           on a particular register (extremely unusual), they must set a Const
           zero bit in the vector.
     """
-    def __init__(self, wid, fu_vecs):
-        self.reg_width = wid
+    def __init__(self, dep, fu_vecs, sync=False):
+        self.reg_dep = dep
         # inputs
         self.fu_vecs = fu_vecs
+        self.sync = sync
         for v in fu_vecs:
-            assert len(v) == wid, "FU Vector must be same width as regfile"
+            assert len(v) == dep, "FU Vector must be same width as regfile"
 
-        self.g_pend_o = Signal(wid, reset_less=True)  # global pending vector
+        self.g_pend_o = Signal(dep, reset_less=True)  # global pending vector
 
     def elaborate(self, platform):
         m = Module()
 
         pend_l = []
-        for i in range(self.reg_width): # per-register
+        for i in range(self.reg_dep): # per-register
             vec_bit_l = []
             for v in self.fu_vecs:
                 vec_bit_l.append(v[i])             # fu bit for same register
             pend_l.append(Cat(*vec_bit_l).bool())  # OR all bits for same reg
-        m.d.comb += self.g_pend_o.eq(Cat(*pend_l)) # merge all OR'd bits
+        if self.sync:
+            m.d.sync += self.g_pend_o.eq(Cat(*pend_l)) # merge all OR'd bits
+        else:
+            m.d.comb += self.g_pend_o.eq(Cat(*pend_l)) # merge all OR'd bits
 
         return m
 
@@ -69,13 +71,13 @@ def g_vec_sim(dut):
     yield
     yield dut.issue_i.eq(0)
     yield
-    yield dut.go_read_i.eq(1)
+    yield dut.go_rd_i.eq(1)
     yield
-    yield dut.go_read_i.eq(0)
+    yield dut.go_rd_i.eq(0)
     yield
-    yield dut.go_write_i.eq(1)
+    yield dut.go_wr_i.eq(1)
     yield
-    yield dut.go_write_i.eq(0)
+    yield dut.go_wr_i.eq(0)
     yield
 
 def test_g_vec():