self.wid = wid
# inputs
self.i = Signal(wid, reset_less=True)
- self.o = Signal(wid, reset_less=True)
+ self.o = Signal(wid, reset_less=True)
def elaborate(self, platform):
m = Module()
m.d.comb += t.eq(self.i[i])
else:
m.d.comb += t.eq(~Cat(ni[i], *self.i[:i]).bool())
-
+
# we like Cat(*xxx). turn lists into concatenated bits
m.d.comb += self.o.eq(Cat(*res))
def __iter__(self):
yield self.i
yield self.o
-
+
def ports(self):
return list(self)
yield self.req_rel_i
yield self.go_rd_o
yield self.go_wr_o
-
+
def ports(self):
return list(self)