class LDSTDepCell(Elaboratable):
""" implements 11.4.12 mitch alsup load/store dependence cell, p45
-
- note: the load-hold-store / store-hold-load both come through from
- the previous cell and accumulate using ORing to create priority
- picking (in the sparse-matrix, which is where the cells are wired up)
"""
def __init__(self):
# inputs
self.load_hit_i = Signal(reset_less=True) # load hit in (right)
self.stwd_hit_i = Signal(reset_less=True) # store w/ data hit in (right)
- self.ld_hold_st_i = Signal(reset_less=True) # load holds st in (right)
- self.st_hold_ld_i = Signal(reset_less=True) # st holds load in (right)
# outputs (latched rd/wr pend)
self.ld_hold_st_o = Signal(reset_less=True) # load holds st out (left)
m.d.comb += raw_l.r.eq(self.stor_i) # reset on ST
# Hold results (read out horizontally, accumulate in OR fashion)
- lhs = war_l.qn & self.load_hit_i
- shl = raw_l.qn & self.stwd_hit_i
- m.d.comb += self.ld_hold_st_o.eq(self.ld_hold_st_i | lhs)
- m.d.comb += self.st_hold_ld_o.eq(self.st_hold_ld_i | shl)
+ m.d.comb += self.ld_hold_st_o.eq(war_l.qn & self.load_hit_i)
+ m.d.comb += self.st_hold_ld_o.eq(raw_l.qn & self.stwd_hit_i)
return m
yield self.issue_i
yield self.load_hit_i
yield self.stwd_hit_i
- yield self.ld_hold_st_i
- yield self.st_hold_ld_i
yield self.ld_hold_st_o
yield self.st_hold_ld_o