+""" Mitch Alsup 6600-style LD/ST scoreboard Dependency Cell
+
+Relevant bugreports:
+* http://bugs.libre-riscv.org/show_bug.cgi?id=81
+
+"""
+
from nmigen.compat.sim import run_simulation
from nmigen.cli import verilog, rtlil
from nmigen import Module, Signal, Elaboratable
def elaborate(self, platform):
m = Module()
- m.submodules.war_l = war_l = SRLatch() # Write After Read Latch
- m.submodules.raw_l = raw_l = SRLatch() # Read After Write Latch
+ m.submodules.war_l = war_l = SRLatch(sync=False) # WriteAfterRead Latch
+ m.submodules.raw_l = raw_l = SRLatch(sync=False) # ReadAfterWrite Latch
+ # issue & store & load - used for both WAR and RAW Setting
i_s_l = Signal(reset_less=True)
-
m.d.comb += i_s_l.eq(self.issue_i & self.stor_i & self.load_i)
+
# write after read latch: loads block stores
m.d.comb += war_l.s.eq(i_s_l)
- m.d.comb += war_l.r.eq(self.load_i)
+ m.d.comb += war_l.r.eq(self.load_i) # reset on LD
# read after write latch: stores block loads
m.d.comb += raw_l.s.eq(i_s_l)
- m.d.comb += raw_l.r.eq(self.stor_i)
+ m.d.comb += raw_l.r.eq(self.stor_i) # reset on ST
- # Hold results (read out horizontally)
- m.d.comb += self.ld_hold_st_o.eq(war_l.qn | self.load_hit_i)
- m.d.comb += self.st_hold_ld_o.eq(raw_l.qn | self.stwd_hit_i)
+ # Hold results (read out horizontally, accumulate in OR fashion)
+ m.d.comb += self.ld_hold_st_o.eq(war_l.qn & self.load_hit_i)
+ m.d.comb += self.st_hold_ld_o.eq(raw_l.qn & self.stwd_hit_i)
return m