add bus.err to list of default Wishbone signals in Tercel

[soc.git] / src / soc / bus / tercel.py

diff --git a/src/soc/bus/tercel.py b/src/soc/bus/tercel.py
index a927ef25b7cbccdc0305b1e3d59c9ce1a602c24f..102218236a5faa2830ff8e83395798fc741b7aa2 100644 (file)
--- a/src/soc/bus/tercel.py
+++ b/src/soc/bus/tercel.py
@@ -15,6 +15,7 @@ from nmigen_soc.wishbone.bus import Interface
 from nmigen_soc.memory import MemoryMap
 from nmigen.utils import log2_int
 from nmigen.cli import rtlil, verilog
+from nmutil.byterev import byte_reverse
 import os
 
 __all__ = ["Tercel"]
@@ -45,11 +46,11 @@ class Tercel(Elaboratable):
         # TODO, sort this out.
         assert clk_freq is not None
         clk_freq = round(clk_freq)
-        self.clk_freq = Const(clk_freq, clk_freq.bit_length())
+        self.clk_freq = Const(clk_freq, 32) #clk_freq.bit_length())
 
         # set up the wishbone busses
         if features is None:
-            features = frozenset()
+            features = frozenset({'err'})
         if bus is None:
             bus = Interface(addr_width=spi_region_addr_width,
                             data_width=data_width,
@@ -107,6 +108,16 @@ class Tercel(Elaboratable):
         # wb address is in words, offset is in bytes
         comb += spi_bus_adr.eq(bus.adr - (self.adr_offset >> 2))
 
+        # urrr.... byte-reverse the config bus and data bus read/write
+        cdat_w = Signal.like(cfg_bus.dat_w)
+        cdat_r = Signal.like(cfg_bus.dat_r)
+        dat_w = Signal.like(bus.dat_w)
+        dat_r = Signal.like(bus.dat_r)
+        comb += cdat_w.eq(byte_reverse(m, "rv_cdat_w", cfg_bus.dat_w, 4))
+        comb += cfg_bus.dat_r.eq(byte_reverse(m, "rv_cdat_r", cdat_r, 4))
+        comb += dat_w.eq(byte_reverse(m, "rv_dat_w", bus.dat_w, 4))
+        comb += bus.dat_r.eq(byte_reverse(m, "rv_dat_r", dat_r, 4))
+
         # create definition of external verilog Tercel code here, so that
         # nmigen understands I/O directions (defined by i_ and o_ prefixes)
         idx, bus = self.idx, self.bus
@@ -120,23 +131,25 @@ class Tercel(Elaboratable):
 
                             # SPI region Wishbone bus signals
                             i_wishbone_adr=spi_bus_adr,
-                            i_wishbone_dat_w=bus.dat_w,
+                            i_wishbone_dat_w=dat_w,
                             i_wishbone_sel=bus.sel,
-                            o_wishbone_dat_r=bus.dat_r,
+                            o_wishbone_dat_r=dat_r,
                             i_wishbone_we=bus.we,
                             i_wishbone_stb=bus.stb,
                             i_wishbone_cyc=bus.cyc,
                             o_wishbone_ack=bus.ack,
+                            o_wishbone_err=bus.err,
 
                             # Configuration region Wishbone bus signals
                             i_cfg_wishbone_adr=cfg_bus.adr,
-                            i_cfg_wishbone_dat_w=cfg_bus.dat_w,
+                            i_cfg_wishbone_dat_w=cdat_w,
                             i_cfg_wishbone_sel=cfg_bus.sel,
-                            o_cfg_wishbone_dat_r=cfg_bus.dat_r,
+                            o_cfg_wishbone_dat_r=cdat_r,
                             i_cfg_wishbone_we=cfg_bus.we,
                             i_cfg_wishbone_stb=cfg_bus.stb,
                             i_cfg_wishbone_cyc=cfg_bus.cyc,
                             o_cfg_wishbone_ack=cfg_bus.ack,
+                            o_cfg_wishbone_err=cfg_bus.err,
 
                             # QSPI signals
                             o_spi_d_out=self.dq_out,
@@ -162,7 +175,7 @@ class Tercel(Elaboratable):
             comb += pins.cs.eq(~self.cs_n_out)
             # ECP5 needs special handling for the SPI clock, sigh.
             if self.lattice_ecp5_usrmclk:
-                self.specials += Instance("USRMCLK",
+                m.submodules += Instance("USRMCLK",
                     i_USRMCLKI  = self.spi_clk,
                     i_USRMCLKTS = 0
                 )