add XLEN option to regfiles via pspec

[soc.git] / src / soc / bus / test / test_minerva.py

diff --git a/src/soc/bus/test/test_minerva.py b/src/soc/bus/test/test_minerva.py
index 299c93791b601011f78bcbbd091538cb379a3f0a..4e59437ec7a6e20bd7f4c72c6c54dee8a249098f 100644 (file)
--- a/src/soc/bus/test/test_minerva.py
+++ b/src/soc/bus/test/test_minerva.py
@@ -1,28 +1,81 @@
-from nmigen_soc.wishbone.sram import SRAM
+from soc.bus.sram import SRAM
 from nmigen import Memory, Signal, Module
 from soc.minerva.units.loadstore import BareLoadStoreUnit, CachedLoadStoreUnit
+from soc.minerva.units.fetch import BareFetchUnit, CachedFetchUnit
 
 
 class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit):
-    def __init__(self, addr_wid=64, mask_wid=4, data_wid=64):
-        super().__init__(addr_wid, mask_wid, data_wid)
+    def __init__(self, pspec):
+        super().__init__(pspec)
+        pspec = self.pspecslave
+        # small 32-entry Memory
+        if (hasattr(pspec, "dmem_test_depth") and
+                isinstance(pspec.dmem_test_depth, int)):
+            depth = pspec.dmem_test_depth
+        else:
+            depth = 32
+        print("TestSRAMBareLoadStoreUnit depth", depth)
+
+        self.mem = Memory(width=pspec.reg_wid, depth=depth)
 
     def elaborate(self, platform):
         m = super().elaborate(platform)
         comb = m.d.comb
-        # small 32-entry Memory
-        memory = Memory(width=self.addr_wid, depth=32)
-        m.submodules.sram = sram = SRAM(memory=memory, granularity=8,
+        m.submodules.sram = sram = SRAM(memory=self.mem, granularity=8,
                                         features={'cti', 'bte', 'err'})
-        dbus = self.dbus
+        dbus = self.slavebus
 
         # directly connect the wishbone bus of LoadStoreUnitInterface to SRAM
         # note: SRAM is a target (slave), dbus is initiator (master)
-        fanouts = ['adr', 'dat_w', 'sel', 'cyc', 'stb', 'we', 'cti', 'bte']
+        fanouts = ['dat_w', 'sel', 'cyc', 'stb', 'we', 'cti', 'bte']
         fanins = ['dat_r', 'ack', 'err']
         for fanout in fanouts:
+            print("fanout", fanout, getattr(sram.bus, fanout).shape(),
+                  getattr(dbus, fanout).shape())
+            comb += getattr(sram.bus, fanout).eq(getattr(dbus, fanout))
             comb += getattr(sram.bus, fanout).eq(getattr(dbus, fanout))
         for fanin in fanins:
             comb += getattr(dbus, fanin).eq(getattr(sram.bus, fanin))
+        # connect address
+        comb += sram.bus.adr.eq(dbus.adr)
+
+        return m
+
+
+class TestSRAMBareFetchUnit(BareFetchUnit):
+    def __init__(self, pspec):
+        super().__init__(pspec)
+        # default: small 32-entry Memory
+        if (hasattr(pspec, "imem_test_depth") and
+                isinstance(pspec.imem_test_depth, int)):
+            depth = pspec.imem_test_depth
+        else:
+            depth = 32
+        print("TestSRAMBareFetchUnit depth", depth)
+        self.mem = Memory(width=self.data_wid, depth=depth)
+
+    def _get_memory(self):
+        return self.mem
+
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+        comb = m.d.comb
+        m.submodules.sram = sram = SRAM(memory=self.mem, read_only=True,
+                                        features={'cti', 'bte', 'err'})
+        ibus = self.ibus
+
+        # directly connect the wishbone bus of FetchUnitInterface to SRAM
+        # note: SRAM is a target (slave), ibus is initiator (master)
+        fanouts = ['dat_w', 'sel', 'cyc', 'stb', 'we', 'cti', 'bte']
+        fanins = ['dat_r', 'ack', 'err']
+        for fanout in fanouts:
+            print("fanout", fanout, getattr(sram.bus, fanout).shape(),
+                  getattr(ibus, fanout).shape())
+            comb += getattr(sram.bus, fanout).eq(getattr(ibus, fanout))
+            comb += getattr(sram.bus, fanout).eq(getattr(ibus, fanout))
+        for fanin in fanins:
+            comb += getattr(ibus, fanin).eq(getattr(sram.bus, fanin))
+        # connect address
+        comb += sram.bus.adr.eq(ibus.adr)
 
         return m