add XLEN option to regfiles via pspec

[soc.git] / src / soc / bus / test / test_minerva.py

diff --git a/src/soc/bus/test/test_minerva.py b/src/soc/bus/test/test_minerva.py
index 93434d6ef814ad436adef707eaefac3639227bdf..4e59437ec7a6e20bd7f4c72c6c54dee8a249098f 100644 (file)
--- a/src/soc/bus/test/test_minerva.py
+++ b/src/soc/bus/test/test_minerva.py
@@ -1,4 +1,4 @@
-from nmigen_soc.wishbone.sram import SRAM
+from soc.bus.sram import SRAM
 from nmigen import Memory, Signal, Module
 from soc.minerva.units.loadstore import BareLoadStoreUnit, CachedLoadStoreUnit
 from soc.minerva.units.fetch import BareFetchUnit, CachedFetchUnit
@@ -7,30 +7,31 @@ from soc.minerva.units.fetch import BareFetchUnit, CachedFetchUnit
 class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit):
     def __init__(self, pspec):
         super().__init__(pspec)
-
-    def elaborate(self, platform):
-        m = super().elaborate(platform)
-        comb = m.d.comb
+        pspec = self.pspecslave
         # small 32-entry Memory
         if (hasattr(pspec, "dmem_test_depth") and
-            isinstance(pspec.dmem_test_depth, int)):
+                isinstance(pspec.dmem_test_depth, int)):
             depth = pspec.dmem_test_depth
         else:
             depth = 32
-        print ("TestSRAMBareLoadStoreUnit depth", depth)
+        print("TestSRAMBareLoadStoreUnit depth", depth)
 
-        self.mem = memory = Memory(width=self.data_wid, depth=depth)
-        m.submodules.sram = sram = SRAM(memory=memory, granularity=8,
+        self.mem = Memory(width=pspec.reg_wid, depth=depth)
+
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+        comb = m.d.comb
+        m.submodules.sram = sram = SRAM(memory=self.mem, granularity=8,
                                         features={'cti', 'bte', 'err'})
-        dbus = self.dbus
+        dbus = self.slavebus
 
         # directly connect the wishbone bus of LoadStoreUnitInterface to SRAM
         # note: SRAM is a target (slave), dbus is initiator (master)
         fanouts = ['dat_w', 'sel', 'cyc', 'stb', 'we', 'cti', 'bte']
         fanins = ['dat_r', 'ack', 'err']
         for fanout in fanouts:
-            print ("fanout", fanout, getattr(sram.bus, fanout).shape(),
-                                     getattr(dbus, fanout).shape())
+            print("fanout", fanout, getattr(sram.bus, fanout).shape(),
+                  getattr(dbus, fanout).shape())
             comb += getattr(sram.bus, fanout).eq(getattr(dbus, fanout))
             comb += getattr(sram.bus, fanout).eq(getattr(dbus, fanout))
         for fanin in fanins:
@@ -46,11 +47,11 @@ class TestSRAMBareFetchUnit(BareFetchUnit):
         super().__init__(pspec)
         # default: small 32-entry Memory
         if (hasattr(pspec, "imem_test_depth") and
-            isinstance(pspec.imem_test_depth, int)):
+                isinstance(pspec.imem_test_depth, int)):
             depth = pspec.imem_test_depth
         else:
             depth = 32
-        print ("TestSRAMBareFetchUnit depth", depth)
+        print("TestSRAMBareFetchUnit depth", depth)
         self.mem = Memory(width=self.data_wid, depth=depth)
 
     def _get_memory(self):
@@ -68,8 +69,8 @@ class TestSRAMBareFetchUnit(BareFetchUnit):
         fanouts = ['dat_w', 'sel', 'cyc', 'stb', 'we', 'cti', 'bte']
         fanins = ['dat_r', 'ack', 'err']
         for fanout in fanouts:
-            print ("fanout", fanout, getattr(sram.bus, fanout).shape(),
-                                     getattr(ibus, fanout).shape())
+            print("fanout", fanout, getattr(sram.bus, fanout).shape(),
+                  getattr(ibus, fanout).shape())
             comb += getattr(sram.bus, fanout).eq(getattr(ibus, fanout))
             comb += getattr(sram.bus, fanout).eq(getattr(ibus, fanout))
         for fanin in fanins: