add XLEN option to regfiles via pspec

[soc.git] / src / soc / bus / test / test_minerva.py

diff --git a/src/soc/bus/test/test_minerva.py b/src/soc/bus/test/test_minerva.py
index 9e34add2a44c783af46fe2c26a15af680bb39509..4e59437ec7a6e20bd7f4c72c6c54dee8a249098f 100644 (file)
--- a/src/soc/bus/test/test_minerva.py
+++ b/src/soc/bus/test/test_minerva.py
@@ -1,4 +1,4 @@
-from nmigen_soc.wishbone.sram import SRAM
+from soc.bus.sram import SRAM
 from nmigen import Memory, Signal, Module
 from soc.minerva.units.loadstore import BareLoadStoreUnit, CachedLoadStoreUnit
 from soc.minerva.units.fetch import BareFetchUnit, CachedFetchUnit