add per-FU PowerDecoders. should now be subsettable

[soc.git] / src / soc / config / ifetch.py

diff --git a/src/soc/config/ifetch.py b/src/soc/config/ifetch.py
index f558d7792c5b9ff9432f9f4c6c358da47f5e0e26..a73a89bc6c5b2fe8962d0072a0b2939010ffd3fe 100644 (file)
--- a/src/soc/config/ifetch.py
+++ b/src/soc/config/ifetch.py
@@ -8,15 +8,16 @@ of unnecessarily-duplicated code
 """
 from soc.experiment.imem import TestMemFetchUnit
 from soc.bus.test.test_minerva import TestSRAMBareFetchUnit
+from soc.minerva.units.fetch import BareFetchUnit
 
 
 class ConfigFetchUnit:
     def __init__(self, pspec):
         fudict = {'testmem': TestMemFetchUnit,
                    'test_bare_wb': TestSRAMBareFetchUnit,
+                   'bare_wb': BareFetchUnit,
                    #'test_cache_wb': TestCacheFetchUnit
                   }
         fukls = fudict[pspec.imem_ifacetype]
-        self.fu = fukls(addr_wid=pspec.addr_wid, # address range
-                          data_wid=pspec.reg_wid)  # data bus width
+        self.fu = fukls(pspec)